Semiconductors

Joint program accelerates EUV mask development for advanced nodes

For more than a decade, IBM has firmly believed that one of the keys to true transistor scaling lies in the adoption of Extreme Ultraviolet (EUV) lithography as a critical patterning technique. This belief culminated in 2015 with IBM’s announcement of the world’s first 7-nanometer-node chip, and again in 2017 with the announcement of a 5nm node chip. In a single exposure step, EUV can create a high-resolution pattern of tens of billions of transistors with one “mask,” which today’s more common semiconductor technology can only attain with patterning processes with multiple masks and prohibitive complexity. Thus, EUV has been critical in enabling scaling for leading-edge logic applications at advanced nodes – like 7nm and 5nm. However, almost every aspect of EUV technology presents new challenges that have to be dealt with in a systematic, collaborative way, and the mask is a critical enabling element.

IBM Research and Photronics, Inc. recently signed a joint research and development agreement to develop manufacturing-grade EUV mask processes for leading-edge logic applications for 7nm, 5nm nodes, and beyond.

Figure 1. A state-of-the-art EUV mask

High-fidelity challenges, high-fidelity results

Masks are designed templates that project or reflect light in a pre-defined pattern onto a silicon wafer, which is used in conjunction with a photo-sensitive film on the wafer to define the circuit designs necessary to build a semiconductor device. EUV operates outside the visible spectrum at 13.5nm wavelength, much shorter than the deep-UV 193nm light of prior technologies. Because of this, much higher fidelity patterns can be achieved, albeit with new mask materials required to capture and create contrast in EUV images. Much like a high-definition television allows you to see many more details in the picture, blemishes and imperfections are also more noticeable with EUV lithography, and they have a disproportionate impact on the ability of an EUV mask to uniformly yield the tens of billions of transistors designed therein.

IBM and Photronics aim to address the specific defect challenges of yielding EUV masks, namely achieving the required pattern fidelity and tolerances to yield 7nm and 5nm devices with EUV, and qualify mask repair processes that will correct critical defects captured in the mask making process. Through this collaborative effort, IBM has already been able to demonstrate yielding baselines for its 7nm and 5nm logic processes at its semiconductor research fab in Albany, NY, and continues to enable critical process and device learning at advanced nodes.

There is no doubt that further refinements in EUV mask architecture and processing will be required to achieve the necessary contrast and pattern fidelity for future scaling. With that goal in mind, IBM and Photronics will use the multi-year collaboration to define and demonstrate the roadmap requirements for EUV masks – a critical element to IBM’s semiconductor research for the next decade.

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