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Research that Matters - HRL Best Paper Award 2005
IBM Haifa Labs
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September 25, 2005
Organized by IBM Research Lab in Haifa, Israel
Coverage directed test generation for functional verification using Bayesian Networks
Avi ziv
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation-based verification (or dynamic verification) by providing a new approach for Coverage-directed Test Generation (CDG). This approach is based on Bayesian networks and computer learning techniques. It provides an efficient way for closing a feedback loop from the coverage domain back to a generator that produces new stimuli to the tested design. This paper also describes how to apply Bayesian networks to the CDG problem. Applying Bayesian networks to the CDG framework has been tested in several experiments, exhibiting encouraging results and indicating that the suggested approach can be used to achieve CDG goals.
The ETSI Extended Distributed Speech Recognition DSR Standards
Alex Sorin
These two papers present work that has been carried out in developing the ETSI Extended DSR standards ES 202 211 and ES 202 212. These standards extend the previous ETSI DSR standards: basic front-end ES 201 108, and advanced (noise robust) front-end ES 202 050, respectively. The extensions enable enhanced tonal language recognition, as well as server-side speech reconstruction capability.
The first paper discusses the client-side estimation of pitch and voicing class parameters. It presents experimental results that show enhancement of tonal language recognition rates of proprietary recognition engines, when the standard extensions are used. The second paper discusses the server-side reconstruction. Experimental results presented in this paper show that the reconstructed speech produced by the standards is highly intelligible under clean and noisy background conditions. The DRT (Diagnostic Rhyme Test) and TT (Transcription Test) scores presented meet or exceed the objective values corresponding to the US DoD (Department of Defense) Federal standard MELP (Mixed-Excitation Linear Predictive) code operating at 2400 bps.
AMiT - the situation manager
Asaf Adi
This paper presents the "situation manager", a tool that includes both a language and an efficient runtime execution mechanism aimed at reducing the complexity of active applications. This tool follows the observation that in many cases, a gap exists between current tools that enable one to react to a single event, following the ECA (event-condition-action) paradigm, and the reality in which a single event may not require any reaction. However, the reaction should be given to patterns over the event history.
The concept of situation presented here extends the concept of composite event in its expressive power, flexibility, and usability. This paper motivates the work, surveys other efforts in this area, and discusses both the language and the execution model.
Searching XML documents via XML fragments
Yosi Mass
Most of the work on XML query and search has stemmed from the publishing and database communities, mostly for the needs of business applications. Recently, the information retrieval community began investigating the XML search issue to answer information discovery needs. Following this trend, we present an approach in which information needs can be expressed in an approximate manner as pieces of XML documents or "XML fragments" of the same nature as the documents that are being searched. We present an extension of the vector space model for searching XML collections via XML fragments and ranking results by relevance, and describe how we have extended a full-text search engine to comply with this model. The value of the proposed method is demonstrated by the relative high precision of our system, which was among the top performers in the recent INEX workshop. Our results indicate that certain queries are more appropriate than others for the extended vector space model. Specifically, queries with relatively specific contexts but vague information needs are best situated to reap the benefit of this model. Finally our results show that one method may not fit all types of queries and that it could be worthwhile to use different solutions for different applications.
Multithreaded Java program test generation
Shmuel Ur
Finding bugs due to race conditions in multi-threaded programs is difficult, mainly because there are many possible interleavings, any one of which may contain a fault.
The methodology presented here for testing multi-threaded programs has minimal impact on the user and is likely to find interleaving bugs. Our method reruns existing tests to detect synchronization faults. We found that a single test executed a number of times in a controlled environment, may be as effective in finding synchronization faults as many different tests. Because tests are very expensive to write and maintain, many resources can be saved using this method. We observed that simply rerunning tests, without ensuring in some way that the interleaving will change, yields almost no benefits. We implemented the methodology in our test generation tool, ConTest. ConTest combines the replay algorithm, which is essential for debugging, with our interleaving test generation heuristics. ConTest also contains an instrumentation engine, a coverage analyzer, and a race detector (not yet completed) that enhance bug detection capabilities. Besides finding bugs, the greatest advantage of ConTest is its minimal effect on the user. When ConTest is combined into the test harness, the user may not even be aware that the tool is being used.
Optimization opportunities created by global data reordering
Maxim Gurevich
Memory access has proven to be one of the bottlenecks in modern architectures. Improving memory locality and eliminating the amount of memory access can help release this bottleneck. We present a method for link-time profile-based optimization by reordering the global data of the program and modifying its code accordingly. The proposed optimization reorders the entire global data of the program, according to a representative execution rate of each instruction (or basic block) in the code. The data reordering is done in a way that enables the replacement of frequently executed Load instructions, which reference the global data, with fast Add Immediate instructions. In addition, the data reordering tries to improve the global data locality and reduce the total size of the global data area. The optimization was implemented into FDPR (Feedback Directed Program Restructuring), a post-link optimizer, which is part of the IBM AIX operating system for the IBM pSeries servers. Our results on SPECint2000 show a significant improvement of up to 11% (average 3%) in execution time, along with a reduction of up to 97.9% (average 83%) in memory references to the global variables via the global data access mechanism of the program.
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