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April 17, 2007
Organized by IBM Research Lab in Haifa, Israel
Program
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Workshop Agenda PDF version for printing (57 KB)
09:15 Arrival
09:30 Welcome, Oded Cohn, HRL
Session 1
Making Better Use of Hardware
09:45 Initial Results of the Performance Implications of Thread Migration on a Chip Multi-Core,
Y. Sazeides*, P. Michaud+, L. He*, D. Fetis+, P. Charalambous*, C. Ioannou*, A. Seznec+ *University of Cyprus, Nicosia, Cyprus +Irisa-Inria, Rennes, France
(Presentation)
10:15 Caravela: A Distributed Stream-based Computing Platform,
Leonel Sousa, Shinichi Yamagiwa, INESC-ID/IST, TULisbon
(Presentation)
10:45 Probabilistic Cache Filtering,
Yoav Etsion, Dror G. Feitelson, Hebrew University, Jerusalem
(Presentation)
11:15 Coffee break
Session 2
Compiler Optimizations
11:35 Data Layout Optimizations in GCC,
Olga Golovanevsky, Razya Ladelsky, IBM HRL
(Presentation)
12:05 SIMDinator: Use of the x86 SIMD Instructions,
David Livshin, DALsoft
(Presentation)
12:35 Issues and Challenges in Compiling for Multiple Forms of Parallelism, in IBM Research Compilers,
Kathryn O'Brien, IBM T.J. Watson Research Center
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13:05 Lunch and informal discussions
14:10 Keynote: A Highly Programmable C/GPU,
Peter Hofstee, IBM Distinguished Engineer, Chief Architect of the Cell Synergistic Processor, Cell Chief Scientist
15:00 Implementation and Validation of a Cell Simulator using UNISIM,
Felipe Cabarcas, Alejandro Rico, David Rodenas, Xavier Martorell, Alex Ramirez, Eduard Ayguade, UPC
(Presentation)
15:30 Coffee break
Session 3
Making Better Use of Parallelism
15:50 CAPSULE: Parallel Execution of Component-based Programs,
Pierre Palatin, Zheng Li, Yves Lhuillier, Olivier Temam, INRIA
(Presentation)
16:20 Using Extremely Fine Granularity Multithreading for Energy Efficient Computing,
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Technion
(Presentation)
16:50 How Many Cores is Too Many Cores?,
Avi Mendelson, Intel
(Presentation)
17:20 Concluding remarks,
David Bernstein, HRL
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