Multi-Cycle Interconnect Synthesis (MCIS) : (data) register tree construction

Abstract

At the chip integration level (or large designs), the signal often travels long distance over multiple clock cycles. In order to meet the timing goal for such long signal paths, designers need to construct multi-level register trees to meet timing constraints with available registers and routing resources. In general, this may be a very time-consuming process with the labor-intensive iterations. Proposed Multi-Cycle Interconnect Synthesis (MCIS) feature automates this process to construct register trees prior to Clock Tree Synthesis step in a typical Physical Synthesis process. A routing layer specific cycle-reach length based virtual timing model which assumes ideal buffering is used to estimate timing. MCIS starts by selecting a feasible routing layer based on the clock cycle constraints for target net sinks. Then a topology-search graph is generated based on reachability analysis at each tree level. Finally, a greedy exact-cover heuristic is used on the generated graph to select candidate registers at each level covering all sinks to construct the desired register tree. Post-processing to fine tune tree structure & quality using local optimization is performed to further improve QoR. Preliminary results highlighting the benefits of the proposed method are presented. The proposed methods show to build the quality tree with much less time compared with the traditional way.