Gate error models for superconducting qubit architectures

Abstract

In current superconducting qubit devices the best gate fidelities are not high enough for practical error correction, and for gates that require error correction an often quoted experimental milestone is a gate error rate of 1e-4. While decoherence is typically the leading order cause of gate error; noise that arises from hardware can also result in gate errors greater than 1e-4. For this milestone to be achievable it is important to identify and minimize all sources of gate error above this threshold. There are many types of two-qubit gates used in superconducting qubits; however, with respect to control hardware these gates can be generalized to fall under two categories: narrow band RF controlled gates, and broadband flux tunable gates. We will present experimentally motivated gate error models that provide insight on how noise from system hardware gives rise to gate errors for these two control types.