S. Cohen, T.O. Sedgwick, et al.
MRS Proceedings 1983
The design and packaging of integrated circuits requires the calculation of capacitances for three-dimensional conductors located on parallel planes. An integral-equation (IE) computer-solution technique is presented, which provides accurate results. The solution technique minimizes computer storage requirements while maintaining calculating efficiency without excessive computation times. Copyright © 1973 by The Institute of Electrical and Electronics Engineers, Inc.
S. Cohen, T.O. Sedgwick, et al.
MRS Proceedings 1983
L.K. Wang, A. Acovic, et al.
MRS Spring Meeting 1993
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ACS Nano