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IEEE Micro
Paper

Coordinating DRAM and last-level-cache policies with the virtual write queue

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Abstract

To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a focus on writes can shorten both read and write average latency, reduce memory power consumption, and improve overall system performance. © 2011 IEEE.

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IEEE Micro

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