Publication
ESSCIRC 2006
Conference paper

A 5GHz+ 128-bit binary floating-point adder for the POWER6 processor

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Abstract

A fast 128-bit end-around carry adder is designed and fabricated as part of the POWER6 floating-point unit in a 65nm SOI process technology. Efficient use of static circuits and careful balance of the look-ahead tree enable our floating-point design to operate beyond 5GHz with 1.1V supply. © 2006 IEEE.

Date

Publication

ESSCIRC 2006