In multi-GHz chip design domains, interconnects are becoming the limiting factor in the performance, energy dissipation, and signal integrity. The demanding requirements from on-chip wiring pose a serious problem, both from the design flow and the modeling aspects. Previous attempts to tackle this problem in analog and mixed signal (AMS) designs and most other silicon chip technologies are based on the post-layout extraction approach, which fails in the multi-GHz domain for several reasons:
- The interconnect impact is considered too late in the design flow, which may cause costly reroutes and redesigns.
- The attempts to develop RCL post-layout extraction methods usually fail to correctly determine the wire inductances, due to an inability to determine the correct current return paths.
- The existing RC(L) extraction tools do not take into account several physical effects such as substrate effects, which can have a significant impact on the design performance.
The other existing solution in typical GaAs based microwave designs models each wire by its full frequency domain S-parameters, which is not practical for larger, silicon-based designs. Besides, this approach impedance matches every wire or device to 50 Ohm, which is not possible in most silicon-based design domains.
In 1998, a team led by David Goren started developing a new approach to the interconnect problem, which was born as an attempt to resolve serious signal integrity issues in certain SiGe technology designs. The idea of the approach is that since inductance-related effects are important only for a relatively small number of critical wires in a given design, these lines can generally be identified at the pre-layout design stages. The critical wires are then designed differently, using a unique set of transmission line devices, called "on-chip T-lines". The team introduced a small set of on-chip T-line configurations that cover most AMS design needs, and developed original semi-analytical models that predict their full frequency-dependent behavior, from DC up to the cut-off frequency of the transistors in the given technology (skin and proximity effects, silicon substrate effects, crossing lines impact, etc.). An extensive set of measurements was performed on a large combination of on-chip T-lines, and showed agreement in the whole range of frequencies from DC up to millimeter wave frequencies (110GHz.for microstrip T-lines).
Until 2004, the team focused on ultra high-speed A&MS designs in IBM SiGe technology, for which the microstrip T-line devices were introduced. Later on, they moved their focus to mainstream high-speed digital designs in CMOS technologies, introducing coplanar T-line devices and compact RC wire models, both of which supporting crossing lines that complement the design solution to be the "Interconnect Design Suite" offering.
As the result of cooperation with the IBM Burlington design enablement department, the T-line devices have become an integral part of IBM design kits (DKs) in SiGe technologies delivered to both external and internal customers. Towards 2002, the microstrip T-lines were already available in almost all SiGe Foundry Design Kits and won numerous customers. This resulted in a Research Division Award in 2002. Since 2005, they have been included in IBM DKs for leading CMOS and SOI technologies. This work resulted in the IBM Research Outstanding Accomplishment Award in 2007.
In addition to the IBM DK activities, the team develops and delivers the T-line models directly to IBM internal customers.
The T-lines give the IBM semiconductor technology a clear competitive advantage over other foundries by providing a comprehensive design solution for on-chip interconnects.
From 2006 through 2010 we developed a design and modeling methodology of vertical interconnects for 3DI applications as a natural progression of an on-chip interconnect-aware design methodology. The models represent frequency-dependent behavior of vertical interconnects by means of multi-segment RLC scalable filter networks. The networks allow for accuracy versus computation efficiency trade-offs, while maintaining correct asymptotic behavior at both high and low frequency limits. During model development, it was shown that the major effect is pronounced, frequency-dependent, silicon substrate induced dispersion and loss effects, which is considered in the TSV Y-element parameters. The dedicated test site has been designed and submitted to fabrication to verify the model by means of S-parameters to hardware measurement results up to 110GHz.