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IBM Research

Coverage Directed test Generation

Functional Coverage

Simulation-based Functional Verification

Functional verification is the process that ensures conformance of the design to its specification. It is widely acknowledged as the bottleneck of a hardware design cycle. To date, up to 70% of the design development time and resources are spent on functional verification. The increasing complexity of hardware designs, combined with shorter time-to-market requirements, raise the need for developing new techniques and methodologies that provide the verification team the means to achieve its goals fast and with limited resources.

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The current practice for functional verification of large and complex hardware designs starts with a definition of a test plan that comprises a large sets of events that the verification team would like to observe during the verification process. The test plan is usually implemented using random test generator that produces test patterns which are fed to a simulator that run tested design, and coverage tools that detect occurrence of events in the test plan, and provide information related to the progress of the test plan (e.g., which events were covered, how many times, etc.) Analysis of the coverage report allows the verification team to modify the directives for the test generators and to better hit areas or specific tasks in the design that are not overed well.

The use of automatic test generation tools can dramatically reduce the amount of manual labor required to implement the test plan. Still, the manual work needed for analyzing the coverage reports and translating them into directives to the test generator can be a bottleneck in the verification process.



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