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An Intelligent Test-Program Generator for Processor Verification

Genesys is a model-based pseudo-random state-of-the-art test generator that dynamically generates tests using a generation-simulation cycle for each instruction. Its primary aim is to enable the implementation of comprehensive verification plans. Genesys gives the user control to guide the generation of test programs, which range from completely deterministic to totally random. The model-based structure of Genesys makes it applicable to any architecture, which is one of its most significant characteristics. Clearly, this structure also makes it easy to implement and maintain common architecture changes and upgrades. Another important asset is the fact that the structure of Genesys allows for the external incorporation of complex testing knowledge, which represents accumulated testing-engineer expertise. Users can add this knowledge in an incremental and localized manner, thereby providing a virtually unlimited generation platform, in terms of scope and smartness.

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