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Floating-Point Test Generator - FPgen

Processor Verification Technologies

FPgen: A Deep-Knowledge Coverage-Driven Floating-Point Test Generator

FPgen is a test generation framework targeted toward verification of the floating-point datapath. FPgen is a generic tool, which targets architectures that comply with the IEEE Standard 754, however, it can also be used for architectures that deviate from the standard.

FPgen provides a convenient platform for biasing and generating operand data for floating-point instructions.

Constraining the input operands of an operation is relatively straightforward. The main strength of FPgen lies in allowing more complex constraints, including:

  1. Constraints on the final result
  2. Constraints on the intermediate result(s)
  3. Constraints on relations between input operands
  4. Constraints on relations between inputs and results
  5. Simultaneous constraints on inputs and results

FPgen's ability to solve such complex constraints is based on a deep understanding of the floating-point semantics.

A floating-point verification plan is an important complement to FPgen's capabilities as a constraint solver. We constructed a generic test-plan (GTP) for floating-point to help verification engineers in the process of FPU verification. This GTP is based on the experience accumulated during the verification of several processors in IBM, along with a deep knowledge and understanding of algorithms and design for the floating-point unit. The GTP contains many interesting cases to be checked in simulation. It is coverage oriented and comprises several coverage models, each targeting a specific part of the FPU, or a particular feature of floating-point. These models are also implemented as input files for FPgen, giving the user a large base with which to begin the verification process.