Paris, France - February 17, 2004; A number of big-name semiconductor companies- with help to the tune of millions of Euros from the European Union-today launched a collaborative research effort, based on the PSL language, aimed at dramatically improving the productivity of chip design methodology.
The result of this research effort, to be known as Prosyd, will give engineers across Europe access to PSL-based tools and methodologies, enabling them to create higher quality electronic systems with faster time to market.
The project was officially launched today at the DATE'04 conference in Paris, an important European event for companies involved in electronic system design and testing methodologies.
The Prosyd methodology will holistically guide engineers, by integrating processes and tools throughout the development process, from specification through design and implementation to verification. The vehicle for achieving this ambitious goal will be the PSL specification language, recently selected by the Accellera EDA standards organization as a basis for an IEEE standard. PSL, based on the Sugar language from IBM, offers a concise and intuitive means for expressing and sharing design intent. The project will facilitate and encourage the use of PSL by developing supporting tools and expediting their large-scale deployment in Europe. This new property-based paradigm will streamline the chip design process enable the development of higher quality electronic systems within shorter design cycles and with lower costs.
The Prosyd partners represent a wide range of expertise in system design and verification, and in particular have collaborated in the standardization of PSL. The project was a joint initiative of researchers from the IBM Research Lab in Haifa and Graz University of Technology in Austria. The participants include a group of leading European systems companies, R&D centers, and universities, including IBM Haifa Research Lab; Infineon Technologies in Munich, Germany; STMicroelectronics laboratories in UK, Italy and France; the Technical University of Graz in Austria; ITC-IRST in Trento; Verimag in France; the Weizmann Institute of Science in Israel; and the Accellera EDA standards organization.
"Microelectronics technology is advancing so rapidly that present-day systems are now heading towards gate counts of 109," said Dr. Yaron Wolfsthal, senior manager for Formal Verification and Testing Technologies at the IBM Haifa lab, where Sugar was conceived. "With the strong Prosyd team, we'll be able to alleviate problems in the design flow of such large systems by integrating and unifying the many aspects of system development-including requirement definition, design, implementation, and verification."
The prime deliverable of the PROSYD project will be a reference methodology and a set of coherent PSL-based tools for property-based system design. Using these tools, the companies who participate in the project aim to demonstrate an improvement of at least 30% in design productivity. In addition, the companies expect to see an increase in the quality of their chips, resulting in a significant decrease in the number of design flaws that make it through the verification phase.
Initial funding for the Prosyd project is 7 million euros (about $8.7M), of which 4M euros coming from EU funds. The project will last 3 years. A large portion of the activity will be dedicated to marketing and dissemination of the tools and methodologies developed by the project team. It is being supported by the Information Society Technology (IST) sub-program of the European Union's sixth framework of research, and is coordinated by Dr. Daniel Geist of IBM Haifa Research Laboratory.
For more information, visit:
Prosyd homepage: http://www.prosyd.org/
PSL/Sugar Consortium website: http://www.pslsugar.org/
Sugar web pages: http://www.haifa.il.ibm.com/projects/verification/sugar/