System Verification Technologies
The demand for high performance hardware systems with limited power consumption is increasing the complexity of their design and architecture. Modern architectures are heterogeneous by nature and include many cores, general purpose and special purpose processors, accelerators, and complex IO adapters and interconnects. This ever-increasing complexity imposes an extremely difficult challenge on verification, which consumes up to 70% of the design effort.
In an attempt to provide best-of-breed solutions to this area, the System Verification Technologies group focuses on finding effective ways to verify the design of full systems. Our technology and tools support simulation-based verification of a large variety of system designs, ranging from gaming consoles (MS X-Box, Sony PS/3, and Wii) to very large, high-end, computer systems used by enterprises such as System p (the leading UNIX server) and System z (the leading mainframe computer).
Our main technology is X-Gen, a constrained-random stimuli generator for system verification. X-Gen supports a rich test-template language for describing system-level scenarios. Through this language, users may direct the tool to generate scenarios that range from specific to completely random, guided by encapsulated testing knowledge. X-Gen employs AI techniques, such as knowledge representation and constraint satisfaction problems, to tackle the challenge of system-level test generation. X-Gen provides a GUI for editing test-template files and a powerful modeling platform that allows easy introduction of new interactions and components to the system.
We've recently started working on a solution to a growing pain in the domain of pervasive sequences. These sequences, which are part of the system's firmware code, are in charge of the IPL (boot), as well as powering on (and off) chips during normal operation of a server, using the internal debug logic etc. This highly innovative solution will allow the firmware teams to formally specify the sequences, and also allow the hardware teams to model the relevant aspects of the pervasive logic. Based on these formal definitions, the tool will provide services such as generating the actual sequences code (to be part of the product), validating sequences, and generating variants of the sequences for verification purposes.
In addition to the above, we are also involved in developing specialized solutions for challenges faced by our partners in the IBM verification community. For example, we recently completed the development of a pre-silicon verification solution that runs on AWAN*, IBM's RTL simulation accelerator, to be used for the verification of the PCIE logic of the next System z server.
All of our technologies are developed in close cooperation with verification teams in different IBM sites (Austin, Rochester, Raleigh, Boeblingen, and Bangalore).
Despite the improvements in both dynamic and formal pre-silicon verification tools, post-silicon functional validation remains a crucial step in ensuring the functional correctness of the design.
We aim to establish a unified verification methodology, spanning pre-silicon RTL simulation, acceleration, and functional validation on actual silicon.
As part of this work, we have developed Threadmill, a bare-metal user-directed exerciser for acceleration and silicon-based verification.