Program Day 3 - Thursday 7/11/2013


08:30 Registration

09:00 Keynote: Challenges in Enabling the Next Generation Mobile Experience: Are you Ready?,
Scott Runner Qualcomm, USA

10:00 Break

10:15 Session 6: Abstractions
Chair: Ofer Strichman

10:15 Domain Types: Abstract-Domain Selection Based on Variable Usage,
Sven Apel, Dirk Beyer, Karlheinz Friedberger, Franco Raimondi, and Alexander von Rhein

10:40 Efficient Analysis of Reliability Architectures via Predicate Abstraction,
Marco Bozzano, Alessandro Cimatti, and Cristian Mattarei

11:05 Lazy Symbolic Execution Through Abstraction and Sub-Space Search,
Guodong Li and Indradeep Ghosh

11:30 SPIN as a Linearizability Checker under weak memory models,
Oleg Travkin, Annika Mütze, and Heike Wehrheim

11:55 Break

12:30 Session 7: Model Representations
Chair: Karen Yorav

12:30 Arithmetic Bit-level Verification Using Network Flow Model,
Maciej Ciesielski, Walter Brown, and Andre Rossi

12:55 Performance Evaluation of Process Partitioning using Probabilistic Model Checking,
Saddek Bensalem, Borzoo Bonakdarpour, Marius Bozga, Doron Peled, and Jean Quilbeuf

13:20 Improving Representative Computation in ExpliSAT (Tools and experience paper),
Sitvanit Ruah, Hana Chockler, and Dmitry Pidan

13:30 Lunch

14:30 Industry Special Session
Chair: Amir Nahir
This special session brings experts from the industry to share their hands-on experience with some of the rising challenges in verification. The session will cover topics such as: post-silicon validation of mobile devices, system-level verification, and the verification challenges of SoC integration. This session is intended for people from industry, who will hear about other companies' challenges and solutions, and academics, who can gain insight into what the industry is struggling with.

14:30 - 15:00 Moving Validation from CPU to highly integrated mobile devices. Challenges and Solutions,
William Lindsay, Intel, US

Abstract: Intel has moved from delivering single CPU's to fully integrated SOCs with multiple 3rd party IP's. This talk will discuss the challenges and some of Intel's solutions.

Bio: TBD

15:00 - 15:30 System Level Challenges,
Kobi Pines, Marvell, Israel

Abstract: In 1965, Gordon Moore, Intel's co-founder, noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months. Moore's law, however, did not get beyond the silicon. 50 years later it seems that other forces such as packaging technology, S/W engineering and market demands boost Moore's law to outpace even the most optimistic forecasts. On the other hand, in the world of chip design, verification became a commodity. Modern verification, using functional-coverage driven constrained-based random-test generation, is over 15 years old and available today for all using standard language (SystemVerilog) and standard methodology (UVM).

This talk presents the challenges of system level validation and the limitations of 'Modern Verification' methodology coping with system complexity in a world where the single chip is only a small piece of a larger puzzle. The talk also suggests a new top-down paradigm for chip verification that is an integral part of the system validation.

Bio: TBD

15:30 - 16:00 Distributed SoC Project Integration Challenges,
Ohad Tsadik, Broadcom, Israel

Abstract: Standardization process of verification methodologies is going on for more than 10 years now. While EDA vendors and industry leads had recently converged on UVM, users have vast legacy verification infrastructure using different languages and concepts. Essentially, verification process should serve chip design challenges and market demands. Chip execution teams are expected to leverage the legacy while constantly improving results and efficiency. Hence, aspiration to do a "clean" transition to UVM is not practical. For that matter, standardization had recreated the problems it intended to solve. Once again, functional verification leads need to focus on the tools rather than the actual verification goals and product quality.

This talk presents the functional verification challenges of an SoC done in a global company involving multiple multinational teams. Such SoC typically integrates many IP cores originated from the different R&D groups that may have utilized different methodologies, HVL's, and tools. Also, the talk will shortly present emerging solutions designed to deal with those challenges.

Bio: TBD

16:00 Break

16:15 HVC Award Session

17:00 Closing Remarks

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Invited keynote speakers


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