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09:00 Welcome,
Michael Rodeh, VP, IBM, Shmuel Ur, program chair, and Irith Hartman, Scientific Manager, Caesarea Rothschild Institute
The towering verification problem: challenges and solutions
Session chair: Eyal Bin
09:30 Path-based System-level Stimuli Generation,
Shady Copty, Yoav Katz, Itai Jaeger, and Michael Vinov, IBM Haifa Labs
(Presentation)
10:00 Conflicting Directions in Hierarchical Verification,
Yoav Hollander, Verification Division chief technology officer, Cadence
10:45 Multi-core Systems,
Michael Rosenfield, Director of VLSI Systems, IBM Research
11:15 Break
Temporal specifications
Session chair: Karen Yorav
11:45 Synthesis of Designs from Temporal Specifications,
Amir Pnueli, Courant Institute of mathematical Sciences and the Weizmann Institute
(Presentation)
12:30 The Safety Simple Subset,
Shoham Ben-David, University of Waterloo, Dana Fisman, Weizmann Institute of Science, and Sitvanit Ruah, IBM Haifa Labs
(Paper , Presentation)
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13:00 PROSYD: PSL-based Methods for Specification, Design and Verification,
Cindy Eisner, IBM Haifa Labs
13:30 Lunch
From a case for on-line verification toward a case study
Session chair: Yaron Wolfsthal
14:30 Keynote: A Case for Runtime Validation of Hardware,
Sharad Malik, Princeton University
(Presentation)
15:30 Assertion-based Verification for the SpaceCAKE Multiprocessor - A Case Study,
Milind Kulkarni and Benita Bommij, Philips Research India
(Paper , Presentation)
16:00 Break
SAT-based verification
Session chair: Daniel Kroening, Computer Systems Institute, ETH Zuerich
16:30 Simultaneous SAT-based Model Checking of Safety Properties,
Zurab Khasidashvili, Alexander Nadel, Amit Palti, and Ziyad Hanna, Design Technology Solutions, INTEL Corporation, Tel Aviv University
(Paper , Presentation)
17:00 A Decision Heuristic Based on an Abstraction/Refinement Model,
Roman Gershman and Ofer Strichman, Technion - Israel Institute of Technology
(Paper , Presentation)
17:30 Conclusion
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