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IBM Research

Compiler and Architecture Seminar 2005

IBM Haifa Labs

Invitation Program Registration Abstracts

December 12, 2005
Organized by IBM Research Lab in Haifa, Israel

Seminar's Agenda PDF version for printing (43 KB)

09:15 Arrival

09:30 Welcome,
Oded Cohn, Director, IBM Haifa Labs

09:45 Machine Learning Based Adaptive Optimizations,
Mike O'Boyle, University of Edinburgh, UK

10:15 Designing a Language and a Representation for Semi-automatic Program Transformation and Program Generation,
Albert Cohen, INRIA, France

10:45 Multi-platform Auto-vectorization,
Dorit Naishlos, IBM HRL and Richard Henderson, RedHat

11:15 Coffee Break

11:35 Trace Cache Sampling Filter,
Michael Behar, Technion; Avi Mendelson, Intel; Avinoam Kolodny, Technion

12:05 Performance, Power Efficiency, and Scalability of Asymmetric Cluster Chip Multiprocessors,
Tomer Y. Morad, Technion; Uri C. Weiser, Intel; Avinoam Kolodny, Technion; Mateo Valero, UPC, Spain; Eduard Ayguade, UPC, Spain

12:35 The Molen Compiler Backend for Reconfigurable Architectures,
Elena Moscu, Koen Bertels, Stamatis Vassiliadis, TU Delft, The Netherlands

13:05 Lunch

14:00 Yonah - the First Intel CMP Architecture for Mobility,
Ronny Ronen, Intel

14:45 Compilation for the Cell processor,
Kevin O'Brien, IBM Watson Research

15:30 Break

15:45 Automatic Parallelization with Hybrid Analysis,
Lawrence Rauchwerger, Texas A&M University

16:15 Experiences with Media-processing and Multi-processing,
Henk Schepers, Philips

16:45 Towards a Source Level Compiler: Source Level Modulo Scheduling,
Yosi Ben-Asher and Danny Meisler, Haifa University

17:15 Concluding Remarks


Related Seminar Links
Visitors information  
Compiler and Architecture Seminar 2004  
Compiler and Architecture Seminar 2003  
Compiler and Architecture Seminar 2002  

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