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The VLIW effort at the
IBM T.J. Watson Research Center
started in 1986, leading to our first publications
[1,
2]
describing a new approach to exploit instruction-level parallelism in
branch-intensive programs. This approach is based on expressing a program
as a sequence of
tree-instructions,
each of which contains a multiway branch and multiple operations, all
executable concurrently. Since then, three generations of a
parallelizing compiler
have been developed, a 8-unit VLIW processor
prototype
was designed and built, a
tree-based VLIW architecture
has been devised, a complete
simulation environment
has been developed, VLIW-based
techniques
have been introduced into existing compilers, and
methods have been devised for
object code translation
from existing architectures into VLIW.
Our recent work
includes open-source DAISY,
a dynamic binary translation project aiming to represent legacy architectures as
a layer of software on a VLIW, and
LaTTe,
a joint Java (TM) JIT compiler
project with Seoul National University,
focusing on research into fast dynamic compilation techniques
and instruction
level parallelism in Java.
Our research activities include:
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The continuing development of compilation techniques
to extract and exploit instruction-level parallelism (ILP) from programs.
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The development of architectures suited to use
the ILP found through the compilation techniques.
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The continuing development of tools and an environment
to simulate/evaluate the potential benefits of VLIW technology.
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The development of solutions to the limitations
traditionally associated with VLIW architectures, such as
- scalable implementations of VLIW;
- static and dynamic object code translation for achieving binary compatibility;
- software and hardware techniques for memory latency reduction.
-
The integration of VLIW-based compilation techniques
into existing compilers for IBM RS/6000 systems.
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![[Tree-instruction image]](Images/tree.gif)
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