 Overview The
performance of modern computer systems is not only determined by
that for CPU processing speed but also by how well they
transfer, hold, and synchronize data objects. This
situation will become more significant in future server and pervasive
systems where there are demanding constraints in terms of
power consumption, size, and cost without compromising
performance and functionality. Here in the hardware arithmetic
project, we focus on these issues from system
and hardware arithmetic point of view.
 Research items
- Quasi-nonvolatile DRAM system
A new memory
system suitable for information caching.
Adaptively prolonged DRAM refresh cycles using
advanced Reed-Solomon error-correcting circuit.
- High-performance error-correction algorithm
Research
on encoding/decoding algorithm of Reed-Solomon codes
and parallel codec architecture for ultra-high performance.
- VLSI design automation
Syntheses, optimization,
and verification of circuits in particular for
Galois field arithmetic.
 Publications
- Y. Katayama, "Trends in Semiconductor
Memories," IEEE Micro p. 10, Nov./Dec.
1997.
- W. K. Luk, Y. Katayama, A. Satoh, S. Munetoh,
"Development of a High Bandwidth Merged
Logic/DRAM Multimedia Chip," IEEE
International Conference on Computer Design, p.
279 Oct. 1997.
- Y. Katayama and S. Morioka,
"Oneshot Reed-Solomon decoder,"
33rd Annual Conference on Information Science
and Systems, pp. 700-705, 1999.
- Y. Katayama and S. Morioka,
"Error Evaluation Algorithm for Oneshot
Reed-Solomon Decoder," 1999 IEEE Information
Theory Workshop, June 1999.
- S. Morioka and Y. Katayama,
"Design Methodology for one-shot Reed-Solomon
Decoder," 1999 IEEE International Conference
on Computer Design.
- Y. Katayama, E. J. Stuckey,
S. Morioka, and Z. Wu, "Fault-Tolerant Refresh
Power Reduction of DRAMs for Quasi-Nonvolatile Data
Retention," 1999 IEEE International Symposium on
Design and Fault Tolerance in VLSI Systems.
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