Keiji Matsumoto

• “Mechanism and Product Branching Ratios of the SiH₃ + SiH₃ Reaction”
  K. Matsumoto, M. Koshi(Univ. of Tokyo), K. Okawa(Univ. of Tokyo) and H. Matsui(Univ. of Tokyo), J. Phys. Chem., 1996, 100, 8796.
• “Photolysis of Disilane at 193nm”
  N. Tada(Univ. of Tokyo), K. Tonokura(Univ. of Tokyo), K. Matsumoto, M. Koshi(Univ. of Tokyo), A. Miyoshi(Univ. of Tokyo) and H. Matsui(Univ. of Tokyo), J. Phys. Chem. A, 1999, 103, 322.
• “Channel Specific Rate Constants Relevant to the Thermal Decomposition of Disilane”
  K. Matsumoto, S. J. Klippenstein(Sandia National Laboratories, US), K. Tonokura(Univ. of Tokyo) and M. Koshi(Univ. of Tokyo), J. Phys. Chem. A, 2005, 109, 4911.
• “Thermal Decomposition Mechanism of Disilane”
  K. Yoshida(Univ. of Tokyo), K. Matsumoto, T. Oguchi(Toyohashi Univ. of Technology), K. Tonokura(Univ. of Tokyo) and M. Koshi(Univ. of Tokyo), J. Phys. Chem. A, 2006, 110, 4726.
• “Reaction Mechanism of Silicon Cat-CVD”
  S. Nakamura (Univ. of Tokyo), K. Matsumoto, A. Susa (Univ. of Tokyo), M. Koshi (Univ. of Tokyo), J. Non-Crystalline Solids, 2006, 352, 919.
• “ Adsorption of Disilyne(Si(H2)Si) and Disilene(H2SiSiH2) on the Si(100)-2×1 surface and on the H-terminated Si(100)-2×1 surface”
  K. Matsumoto and M. Koshi (Univ. of Tokyo), Journal of the Electrochemical Society, 2008, 155, D419.

• “Vertical Electrical Connections for Stacked Reflective Pixel Structures”
  K. Matsumoto, K. Sueoka, K. Takeda, M. Hasegawa, Y. Taira, L. T. Romankiw, P. A. Gruber, J. P. Doyle, International Display Workshop (IDW) 2000 (2000/11/29)
• “Vertical Electrical Connections for Multi-layer Stacked Display”
  K. Matsumoto, K. Takeda, M. Hasegawa, K. Sueoka, International Display Workshop (IDW) 2001 (2001/10/17)
• “Elementary Reactions in Silicon Catalytic CVD Processes”
  K. Matsumoto, S. Nakamura (Univ. of Tokyo), M. Koshi (Univ. of Tokyo), 6th International Conference on Chemical Kinetics(NIST), Gaithersburg,MD (2005/7/25)
• “Reaction Mechanism of Silicon Catalytic CVD Processes”
  S. Nakamura(Univ. of Tokyo), K. Matsumoto, A. Susa (Univ. of Tokyo), M. Koshi(Univ. of Tokyo), 21st International Conference on Amorphous and Nanocrystalline Semiconductors (ICANS21), Lisbon, Portugal (2005/9/7)
• “Gas phase and surface phase chemical kinetics in silicon CVD processes”
  K. Matsumoto, M. Koshi(Univ. of Tokyo), 209th Meeting of the Electrochemical Society, Denver, US (2006/5/7)
• “Gas phase and surface phase chemical kinetics in silicon CVD processes”
  K. Matsumoto, M. Koshi(Univ. of Tokyo), ECS(the Electrochemical Society) Transactions, 2007, 2(7), 107.
• “Investigation of the thermal resistance of a three-dimensional (3D) chip stack from the thermal resistance measurement and modeling of a single-stacked-chip”
  K. Matsumoto, K. Sakuma, F. Yamada and Y. Taira, ICEP 2008 (International Conference on Electronics Packaging 2008), Tokyo, Japan (2008/6/15)
• “Thermal resistance measurements of interconnections, for the investigation of the thermal resistance of a three-dimensional (3D) chip stack”
  K. Matsumoto and Y. Taira, Semi-Therm 2009 (Semiconductor Thermal Measurement and Management Symposium 2009), San Jose, US (2009/3/19)
• “Thermal characterization of a three-dimensional (3D) chip stack”
  K. Matsumoto and Y. Taira, ICEP 2009 (International Conference on Electronics Packaging 2009), Kyoto, Japan (2009/4/15)

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• “Mechanism and Product Branching Ratios of the SiH₃ + SiH₃ Reaction”
  K. Matsumoto M. Koshi(Univ. of Tokyo), K. Okawa(Univ. of Tokyo) and H. Matsui(Univ. of Tokyo), 33th Japanese Symposium on Combustion, Tokyo, Japan (1995/11/27)
• “Channel Specific Rate Constants Relevant to the Thermal Decomposition of Disilane ”
  K. Matsumoto, S. J. Klippenstein(Sandia National Laboratories, US), K. Tonokura(Univ. of Tokyo) and M. Koshi(Univ. of Tokyo), 21st Symposium on Chemical Kinetics and Dynamics, Osaka, Japan (2005/6/2)
• “Elementary Reactions in Silicon Catalytic CVD processes”
  S. Nakamura(Univ. of Tokyo), K. Matsumoto, A. Susa(Univ. of Tokyo) and M. Koshi(Univ. of Tokyo), 21st Symposium on Chemical Kinetics and Dynamics, Osaka, Japan (2005/6/2)
• “Thermal characterization of a three-dimensional (3D) chip stack”
  K. Matsumoto and Y. Taira, Japan Institute of Electronics Packaging, 3D Packaging Working Group Meeting (エレクトロニクス実装学会　3次元実装材料研究会), Tokyo, Japan (2009/2/24)

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