Hiroshi Inoue
Advisory Researcher, IBM Research - Tokyo

in Japanese

• (Sept 20, 2012) I will give an invited talk at VMIL 2012 workshop co-located with OOPSLA.
• (July 6, 2012) My paper titled "Adaptive Multi-Level Compilation in a Trace-based Java JIT Compiler" got accepted to OOPSLA2012 [paper, slides]
• (Mar 24, 2012) My paper titled "Identifying the Sources of Cache Misses in Java Programs Without Relying on Hardware Counters" got accepted to ISMM2012. [paper, slides]
• (July 25, 2011) A paper I coauthored got accepted to OOPSLA2011. (title "Reducing Trace Selection Footprint for Large-scale Java Applications with no Performance Loss") [paper]
• (May 20, 2011) My paper titled "A High-Performance Sorting Algorithm for Multicore SIMD Processors" got accepted for publication by Software: Practice and Experience. [paper]
• (Jan 5, 2011) A paper I coauthored got accepted to ASPLOS2011. (title "Improving the Performance of Trace-based Systems by False Loop Filtering") [paper]

Optimizing compilers, Language runtime systems, Parallel algorithms

Mar. 2000
Bachelor of System Design Engineering, Keio University, Japan
Bachelor thesis: Direct Numerical Simulation of Dispersed Two-Phase Turbulent Flows With Evaporating Droplets
Advisor: Prof. Koichi Hishida

Mar. 2002
Master of System Design Engineering, Keio University, Japan
Master thesis: Turbulence Modification by Dispersed Particles in Two-Phase Turbulent Flows
Advisor: Prof. Koichi Hishida

Apr. 2002 - present
Researcher at IBM Research

Jul. 2008, Yamashita SIG Research Award, Information Processing Society of Japan
Mar. 2000, Graduate with Honors, Keio University

Journal Papers

• Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, and Toshio Nakatani, "A high-performance sorting algorithm for multicore single-instruction multiple-data processors", Software: Practice and Experience, Vol. 42(6), pp. 753-777, 2012.
• Hiroshi Inoue, Hideaki Komatsu, Toshio Nakatani, "Accelerating UTF-8 Decoding Using SIMD Instructions", Information Processing Society of Japan Transactions on Programming, Vol.1 (2), pp. 1-8 , 2008. (in Japanese)
• Moriyoshi Ohara, Hiroshi Inoue, Yukihiko Sohda, Hideaki Komatsu, and Toshio Nakatani, "MPI microtask for programming the Cell Broadband Engine processor", IBM Systems Journals, Vol 45 (1), pp. 85-102, 2006.
• Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, Toshio Nakatani, "A fast sorting algorithm for VMX instruction set", Information Processing Society of Japan Transactions on Advanced Computing Systems, Vol 47 (ACS 14), pp. 105-114, 2006. (in Japanese)
• Hiroshi Inoue, Takao Moriyama, Yasushi Negishi, Moriyoshi Ohara, "CPU resource reservation system for CPU using Simultaneous Multi Thread", Information Processing Society of Japan Transactions on Advanced Computing Systems, Vol.45 (ACS 5), pp. 21-28, 2004. (in Japanese)

Invited talk

• Hiroshi Inoue, "A Trace-based Java JIT Compiler for Large-scale Applications", The 6th workshop on Virtual Machines and Intermediate Languages (VMIL2012). Tucson, Arizona, USA. 2012.

Conference Papers

• Hiroshi Inoue, Hiroshige Hayashizaki, Peng Wu, and Toshio Nakatani, "Adaptive Multi-Level Compilation in a Trace-based Java JIT Compiler", 2012 ACM Object-Oriented Programming, Systems, Languages & Applications (SPLASH/OOPSLA 2012). Tucson, Arizona, USA. pp 179-194, October 19-26, 2012.
• Hiroshi Inoue and Toshio Nakatani, "Identifying the Sources of Cache Misses in Java Programs Without Relying on Hardware Counters", 2012 International Symposium on Memory Management (ISMM 2012). Beijing, China. pp 133-142. June 15-16, 2012.
• Peng Wu, Hiroshige Hayashizaki, Hiroshi Inoue, and Toshio Nakatani, "Reducing Trace Selection Footprint for Large-scale Java Applications with no Performance Loss", 2011 ACM Object-Oriented Programming, Systems, Languages & Applications (SPLASH/OOPSLA 2011). Portland, Oregon, USA. pp 789-804. October 22-27, 2011.
• Hiroshi Inoue, Hiroshige Hayashizaki, Peng Wu, and Toshio Nakatani, "A Trace-based Java JIT Compiler Retrofitted from a Method-based Compiler", 2011 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2011). Chamonix, France. pp. 246-256, April 2-6, 2011.
• Hiroshige Hayashizaki, Peng Wu, Hiroshi Inoue, Mauricio Serrano and Toshio Nakatani, "Improving the Performance of Trace-based Systems by False Loop Filtering", Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2011). Newport Beach, California, USA. pp. 405-418, March 5-11, 2011.
• Hiroshi Inoue and Toshio Nakatani, "Performance of Multi-Process and Multi-Thread Processing on Multi-core SMT Processors", 2010 IEEE International Symposium on Workload Characterization (IISWC 2010). Atlanta, Georgia, USA. pp 209-218. December 2-4, 2010.
• Hiroshi Inoue and Toshio Nakatani, "How a Java VM Can Get More from a Hardware Performance Monitor", ACM SIGPLAN 2009 International Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA 2009). Orlando, Florida, USA. pp. 137-154. October 25-29, 2009.
• Hiroshi Inoue, Hideaki Komatsu, and Toshio Nakatani, "A Study of Memory Management for Web-based Applications on Multicore Processors", ACM SIGPLAN 2009 Conference on Programming Language Design and Implementation (PLDI 2009). Dublin, Ireland. pp. 386-396. June 15-20, 2009.
• Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, and Toshio Nakatani, "AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors", IEEE The Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT 2007). Brasov, Romania. pp. 189-198. Sept. 15-19, 2007.
• Jessica H. Tseng, Hao Yu, Shailabh Nagar, Niteesh Dubey, Hubertus Franke, Pratap Pattnaik, Hiroshi Inoue, and Toshio Nakatani, "Performance Studies of Commercial Workloads on a Multi-core System", 2007 IEEE International Symposium on Workload Characterization (IISWC 2007), 2007.
• Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridharan Iyengar, Leiguang Gong, Hiroshi Inoue, Hideaki Komatsu, Vadim Sheinin, and Shahrokh Daijavad, "Accelerating Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor", 2007 IEEE International Conference on Multimedia and Expo (ICME 2007), 2007.
• Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridharan Iyengar, Leiguang Gong, Hiroshi Inoue, Hideaki Komatsu, Vadim Sheinin, Shahrokh Daijavad, and Bradley Erickson, "Real-time Mutual-information-based Linear Registration on the Cell Broadband Engine Processor", Fourth IEEE Symposium on Biomedical Imaging (ISBI 2007), 2007.
• Motohiro Kawahito, Hideaki Komatsu, Takao Moriyama, Hiroshi Inoue, and Toshio Nakatani, "A New Idiom Recognition Framework for Exploiting Hardware-Assist Instructions", Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XII), 2006.
• Hiroshi Inoue, Yohei Sato, and Koichi Hishida, "Directional Scale Dependency on Force Coupling for Dispersed Two-Phase Turbulent Flows", Second International Symposium on Turbulence and Shear Flow Phenomena (TSFP2), 2001.

Workshop papers

• Peng Wu, Hiroshige Hayashizaki, Hiroshi Inoue, and Toshio Nakatani, "Reducing Trace Selection Footprint for Large-scale Java Applications without Performance Loss", 10th Workshop on Compiler-Driven Performance, 2011.
• Peng Wu, Hiroshige Hayashizaki, and Hiroshi Inoue, "Understand the Building Blocks of Trace Selection for a Trace-driven Language Compiler", 9th Workshop on Compiler-Driven Performance, 2010.
• Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridharan Iyengar, Leiguang Gong, Hiroshi Inoue, Hideaki Komatsu, Vadim Sheinin, and Shahrokh Daijavad, "Accelerating medical image registration on the Cell broadband engine processor", Second Workshop on Real Time and Interactive Digital Media Supercomputing (RIDMS-2), 2007.
• Daniel Citron, Hiroshi Inoue, Takao Moriyama, Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani, "Exploiting the AltiVec Unit for Commercial Applications", Workshop on Computer Architecture Evaluation using Commercial Workloads, 2006.

Other publications

• IBM Whitepaper, "Real-Time Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor", 2007.
• Hiroshi Inoue, Takao Moriyama, Yasushi Negishi, and Moriyoshi Ohara, "CPU Resource Reservation for Simultaneous Multi-Thread Systems", IBM Research Report, 2006.

About my name: My name is so common in Japan that the DBLP entry for "Hiroshi Inoue" includes many papers that are not related to me. The author pages in Google Scholar and MS Academic Search are maintained.

• Editor for IPSJ Magazine (Information Processing Society of Japan, April 2011 - present)
• External review committee member for ASPLOS 2013, PLDI 2013
• External reviewer for ACM TACO, Software: Practice and Experience, ASPLOS, ICS, SYSTOR and so on