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Kohji Takano


Profile

photo image of Kohji Takano
 He received his BS and MS degrees in information science from Tohoku University, Japan, in 1996 and 1998, respectively.
He joined IBM Research, Tokyo Research Laboratory, in 1998, and had involved in cryptographic hardware design and rapid prototyping for verification project.
He is now working on baseband technology research for wireless system.

Major interests

He received his BS and MS degrees in information science from Tohoku University, Japan, in 1996 and 1998, respectively. He joined IBM Research, Tokyo Research Laboratory, in 1998, and had involved in cryptographic hardware design and rapid prototyping for verification project. He is now working on baseband technology research for wireless system.

Articles

Journals

  • Takehito Sasaki, Takahiro Komiya, Koji Takano, Nobuyuki Oba, Hiroaki Kobayashi and Tadao Nakamura, "Time-Division Pseudo Multi-Port Register File with Wave Pipelining," Transactions of the Institute of Electronics, Information and Communication Engineers, Vol.J80-D-I, No.3, pp.223-226, 1997.
  • Akashi Satoh, Kohji Takano and Nobuyuki Ohba, "A Scalable Hardware Architecture for Elliptic Curve Cryptography on GF(p)," Transactions of the Institute of Electronics, Information and Communication Engineers, Vol.J85-A, No.11, pp.1264-1272, 2002. (in japanese)
  • Akashi Satoh and Kohji Takano, "A Scalable Dual-Field Elliptic Curve Cryptographic Processor," IEEE Transactions on Computers, April 2003
  • Nobuyuki Ohba and Kohji Takano, "An SoC design methodology using FPGAs and embedded microprocessors," Design Automation Conference, June 2004
  • Nobuyuki Ohba and Kohji Takano, "Hardware Design Verification Using Signal Transitions and Transactions," Transactions of the Institute of Electronics, Information and Communication Engineers, April, 2006

International Conferences

  • Takehito SASAKI, Takuya NAKAIKE, Koji TAKANO, Masayuki KATAHIRA, Hiroaki KOBAYASHI and Tadao NAKAMURA, "Memory Hierachy Design for Jetpipeline To Execute Scalar and Vector Instructions in Parallel," Proceedings of the second Aizu International Symposium on Parallel Algorithms/Architectures Synthesis, March, 1997
  • Kohji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi and Tadao Nakamura, "Multiport Register File Using Wave Pipelining," 1997 IWLS ( IEEE/ACM International Workshop on Logic Synthesis ), May, 1997
  • Kouji Takano, Takehito SasakiANobuyuki Oba, Hiroaki Kobayashi and Tadao Nakamura, "Automated Design of Wave Pipelined Multiport Register Files Pipelining," Asia and South Pacific Design Automation Conference 1998, February, 1998
  • Kohji Takano, Munetoh Seiji, Nobuyuki Ohba and Shigenori Shimizu, "A Cryptographic Accelerator Card with Small Fast Low-Power RSA Engine," CoolchipsII ( An Internaltional Symposium on Low-Power and High-Speed Chips ), April, 1999
  • Kohji Takano, Munetoh Seiji, Nobuyuki Ohba and Shigenori Shimizu, "TATSU - Hardware accelerator for public-key cryptography using Montgomery method," An Internaltional Symposium on Low-Power and High-Speed Chips, April, 2000
  • Akashi Satoh, Nobuyuki Ohba, Takano Kohji, Edward D'Agignon, "A High-Speed MARS Hardware," National Institute of Standard Technology, May, 2000
  • Kohji Takano, Akashi Satoh, Nobuyuki Ohba, "Hardware Resource and Performance Optimization for Elliptic Curve Cryptography, "
    An Internaltional Symposium on Low-Power and High-Speed Chips IV, April, 2001
  • Akashi Satoh and Kohji Takano, "Low-Power Arithmetic Circuits for Cryptographic Hardware," Austin Conference on Energy-Efficient Design2004, April, 2004
  • Nobuyuki Ohba and Kohji Takano "A Hardware Design Verification Methodology Using Signal Transitions and Transactions," An Internaltional Symposium on Low-Power and High-Speed Chips VIII, April, 2005
  • Nobuyuki Ohba and Kohji Takano, "Hardware Debugging Method Based on Signal Transitions and Transactions," Asia and South Pacific Design Automation Conference 1998, Janualy, 2006
  • Yasuteru Kohda, Kohji Takano, Gang Zhang, and N. Ohba, "P3 - Performance and Power Optimization Tool for Portable Embedded Systems," Internaltional Symposium on Low-Power and High-Speed Chips X, April 2007.
  • Yasuteru Kohda, Kohji Takano, Gang Zhang, and N. Ohba, "A Power Monitoring and Optimization Tool for Mobile Systems," International Symposium on Information and Computer Elements 2007 ,September, 2007.
  • Z. Gang, K.Takano and N. Ohba, "Low Intrusive Real-time Execution Tracer for UML-based Emedded Software, " Internaltional Symposium on Low-Power and High-Speed Chips XI, April 2008.

Awards

  • Best Paper Award for Young Researchers of the National Convention of IPSJ (Information Processing Society of Japan), "Small Hardware Architecture for New Standard Block Cipher AES," The 63rd National Convention of IPSJ.
  • Encouragement Prize at the 18th Workshop on Circuits and Systems in Karuizawa, "Hardware Design Verification Using Signal Transitions and Transactions," The 18th Workshop on Circuits and Systems in Karuizawa.
  • Best Paper Award, "A low-intrusive real-time observation method for tracing function transitions of concurrent programs in embedded systems," Embedded Systems Symposium 2007

Domestic Conferences

Books(Articles)