Moore’s Law: Life in the fast lane
Keeping up with Moore's Law requires constant innovation across many different technologies. Some innovations involve the chips themselves: increasing their speed, decreasing the size of the devices, new packaging styles, and so on. These innovations in turn drive changes in the technologies needed to test and debug the chips. Such tests are critical for identifying failures and faults in chip designs and manufacturing.
New challenges, potential solutions
One chip innovation involves the wires that connect the individual transistors. In earlier generations of chips,one or two layers of wiring connected the transistors, so that most of the transistors and wires were directly visible. Now, however, the wiring on the chip is much more complex, leading to as many as seven levels of wiring. Then the bottom layers of wires and the transistors are almost completely covered by the upper layers of wires. As a result, traditional methods of measuring electrical activity on a chip are becoming impractical. PICA meets this challenge because it can look at the transistors through the backside of a chip, where no metal wires get in the way.
PICA has applications beyond trouble-shooting. IBM has used it to debug chips destined for use in production computers. In the future, the approach could become a standard method of debugging. In addition, PICA’s ability to peer inside chips makes it a significant tool for designers. By examining literally thousands of FETs on individual chips at one time, designers could work out the steps necessary to improve chip performance.
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