Overview

The Silicon-On-Insulator (SOI) technology promises significant performance advantages over more conventional bulk CMOS technologies due to the dramatic reduction of junction capacitance. It also, however, introduces new problems in the design of practical circuits. First, the SOI technology creates parasitic bipolar devices with a design, and these devices can cause improper circuit operation. Second, because the "body" electrode of an SOI device is normally not connected to any fixed potential, that potential can and will vary with time in a way that is dependent upon the switching activity of the device. This, in turn, will cause a shift in the threshold of the device, with concomitant changes in delays. This project is aimed at understanding these phenomena in a manner which enables use of IBM's SOI technology for both high-performance and low-power applications.