Overview

Power4 is the processor that will be used in the next-generation RS/6000 and AS/400 systems (IBM eServer i-series and p-series). It is a high-performance VLSI chip that includes two 64-bit PowerPC microprocessors, connected at high bandwidth to an on-chip memory subsystem consisting of a shared L2-cache memory plus the directory and interface for a large off-chip L3, and with high-speed busses and I/O to enable efficient 8-way systems to be built on a single 4-chip module. The microprocessors will operate at > 1 GHz clock frequency and have processor-L2 cache bandwidths of 100 GB/s. The Power4 chip is divided into 12 units, some of which are being designed by multi-site teams. The Research team focuses on all aspects of VLSI design as well as design tools and methodologies. For the Instruction Fetch and L2 Cache Control Units, the circuit and physical design of the logic circuits (about 2M transistors for each unit) are done in Yorktown, the array designs in Poughkeepsie, and the logic and verification in Austin. Performance exceeding 1GHz is achieved at acceptable power levels using mostly static, custom-designed CMOS circuits for the dataflow. Synthesized logic, implemented using circuit books from a standard cell library, is used for most control circuits. The circuits are designed to be fabricated in IBM's 0.18 CMOS 8S2 Silicon-on-Insulator technology with 7 levels of copper wiring.