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Publications:

Patents

  1. YOR920030455US1 Filed 11/24/2003: Resonant Tree Driven CLock Distribution Grid
  2. YOR920030364US1 Filed 11/13/2003: Clock Gated Power Supply Noise Compensation
  3. YOR920030363US1 Filed 11/13/2003: Built in Self Test Circuit for Measuring Total Timing Uncertainty in a Digital Data Path
  4. YOR92003030303US1 Filed 7/24/2003: System and Method for Derivative-Free Optimization of Electrical Circuits
  5. US6531759: Issued 03/11/2003  Alpha particle shield for integrated circuit
  6. US631759:   Issued 07/09/2002 Efficient Method of Modeling Three-D Interconnect Sructures for Frequency Dependent Crosstalk Simulation
  7. US6342823: Issued 01/29/2002  System and method for reducing calculation complexity of lossy, frequency-dependent transmission-line computation
  8. US6311313: Issued 10/30/2001  X-Y grid tree clock distribution network with tunable tree and grid networks
  9. US6205571: Issued 03/20/2001   X-Y grid tree tuning method
  10. US6006025: Issued 12/21/1999  Method of clock routing for semiconductor chips

  11. US5610528: Issued 03/11/1997  Capacitive bend sensor

Invited: Talks, Papers, and Tutorials

  1. Challenges and Solutions in the Design of High-Frequency Clock Distributions
    Phillip Restle and Ken Shepard
    Tutorial, ICCAD, San Jose, CA, Nov. 11, 2004

  2. IBM Microprocessor Global Clock Directions
  3. Phillip Restle, Invited Talk, Digital Clocking Seminar
    Stanford, CA Stanford Photonics Research Center
    Digital Clocking Seminar
    Dec. 3rd, 2002

  4. ISSCC special evening session on Inductance:  Implications and Solutions for High-Speed Design - Clock Distribution
  5. Phillip Restle, Xuejue Huang
    Invited Talk, ISSCC (session SE1) Digest of Technical Papers pg. 13
    San Francisco, CA, Feb. 3rd, 2002

  6. Technical Visualizations in VLSI Design
  7. PDF file of paper
    Higher resolution controllable animations from talk (and more)
    Phillip Restle
    Design Automation Conference
    Invited Talk
    Las Vegas, California
    June, 2001

  8. On-Chip Wiring Design Challenges for Gigahertz Operation
  9. Alina Deutsch, Paul W. Coteus, Gerard V. Kopcsay, Howard H. Smith, Christopher W. Surovic, Byron L. Krauter Daniel C. Edelstein, and Phillip J. Restle
    Invited Paper, Proceedings of the IEEE, Vol. 89, No. 4, pp. 529-555, June, 2001

  10. Multi-GHz Interconnect Effects in Microprocessors
  11. P. Restle, A. Ruehli, S. Walker,
    International Symposium on Physical Design
    Invited Talk, Sonoma California, April, 2001

  12. Clock Tree and Power Grid Design > 1 GHz
  13. P. Restle, A. Ruehli, S. Walker,
    Advanced Metallization Conference
    Invited Plenary, San Diego, California Oct. 2000

  14. A Clock Distribution Method for Microprocessors
  15. P. Restle et. al.
    Journal of Solid-State Circuits (special issue on the VLSI circuit symposium)
    Vol. 36, pg. 792-799, May 2001.

  16. Multi-GHz Clock Networks Click Here to see Slides and Animations 
  17. Phillip J. Restle,
    IEEE SSCTC Workshop on Design for Multi-GigaHertz Processors,
    San Fransico, Feb. 7, 2000

  18. Dealing with inductance in high-speed chip design
  19. Phillip Restle, Albert Ruehli, Steven G. Walker
    Design Automation Conference pg. 904, embedded tutorial, New Orleans, June, 1999

  20. Interconnect in high speed designs: problems, methodologies and tools
  21. P. J. Restle, J. Phillips, I. Elfadel
    International conference on computer aided design (ICCAD) 
    All-day tutorial, abstract pg. 4 of technical digest, San Jose California, Nov. 1998

  22. Designing the best clock distribution network
  23. P. J. Restle, A. Deutsch
    Symposium on VLSI circuits 
    Keynote, Honolulu Hawaii, June 1998

  24. Designing the best clock distribution network 
  25. P. J. Restle, A. Deutsch
    MIT Microsystems Technology Laboratories Seminar
    Cambridge Massachusets Oct. 6, 1998

  26. Designing the best clock distribution network 
  27. P. J. Restle, A. Deutsch
    Columbia electrical engineering seminar
    New York, New York Dec. 4, 1998

  28. Designing the best clock distribution network 
  29. P. J. Restle, A. Deutsch
    IMAPS advanced technology workshop on next generation package design
    Hilton Head Island, South Carolina, July 1998

  30. Designing the best clock distribution:
  31. optimal vs. practial, humans vs. tools, simple vs. complex LRC models 
    P. J. Restle, IEEE SSCTC international workshop on clock distribution networks 
    Keynote, Atlanta Georgia, October, 1997

Other Publications while at IBM

     
  1. Timing uncertainty measurements on the Power5 microprocessor
    Phillip Restle, Robert L Franch, James K. Norman, William V. Huott, Timothy M. Skergan, Steven C. Wilson, Nicole S. Schwartz, Joachim G. Clabes,
    IEEE ISSCC Digest of Technical Papers, p.354-355, February, 2004

  2. A 4.6 GHz resonant global clock distribution network
    Steven C. Chan, Phillip J. Restle, Norman K. James, Robert L. Franch,
    IEEE ISSCC Digest of Technical Papers, p341-343, February, 2004

  3. Design and implementation of the POWER5 microprocessor
    Joachim Clabes, Joshua Friedrich, Mark Sweet, Jack Dilullo, Sam Chu, Donald Plass, James Dawson, Paul Muench, Larry Powell, Michael Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole Schwartz, Steve Runyon, Gary Gorman, Phillip Restle, Ronald Kalla, Joseph McGill, Steve Dodson, IEEE ISSCC, Feb. 2004, p 55-57.

  4. Design and implementation of the POWER5 microprocessor
    Joachim Clabes et al, Design Automation Conference, 2004, p670-674

  5. Design and implementation of the POWER5 microprocessor
    Joachim Clabes et al, 2004 Internation Conference on Integrated Cirrcuit Design and Technology, ICICDT, 2004 p. 143-145

  6. Design of resonant global clock distributions
    Steven, C. Chan, Kenneth L. Shepard, Phillip J. Restle, IEEE ICCD International Conference on Computer Design: VLSI in Computers and Processors, 2003, p248-253

  7. Loop-based Interconnect Modeling and Optimization Approach for Multi-GHz Clock Network Design
  8. Xuejue Huang, Phillip Restle, Thomas Bucelot, Yu Cao, and Tsu-Jae King and Chenming Hu
    IEEE Journal of solid state circuits
    Vol. 38, No. 3, pg. 457-463, March, 2003

  9. Loop-based Interconnect Modeling and Optimization Approach for Multi-GHz Clock Network Design
  10. Xuejue Huang, Phillip Restle, Thomas Bucelot, Yu Cao, and Tsu-Jae King
    Custom Integrated Circuits Conference (CICC)
    pp. 19-22, 2002, [paper] [slides]

  11. The Clock Distribution of the Power4 Microprocessor
  12. Phillip J. Restle, Craig A. Carter, James P. Eckhardt, Byron L. Krauter, Bradley D. McCredie, Keith A. Jenkins, Alan J. Weger, Anthony V. Mule,
    ISSCC Digest of Technical Papers
    Talk number 8.4, Pg. 144-145, February 2002.

  13. Full-Wave PEEC Time Domain Method for the Modeling of On-Chip Interconnects
  14. Phillip J. Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos
    Transactions on Computer Aided Design
    Vol. 20, pg. 877-887,  July 2001

  15. Physical Design of a Fourth-Generation POWER GHz Microprocessor
  16. C. Anderson et al
    IEEE International Solid-State Circuits Conference
    Technical Digest pg. 232-233
    San Franciso, California
    February, 2001

  17. A Clock Distribution Method for Microprocessors
  18. P. J. Restle, T. G. McNamara, P. J. Camporese, K. F. Eng, K. A. Jenkins, D. H. Allen, M. J. Rohn, M. P. Quaranta, D. W. Boerstler, C. J. Alpert, C. A. Carter, R. N. Bailey, J. G. Petrovik, B. L. Krauter, and B. D. McCredie
    Symposium on VLSI Circuits Technical Digest pp. 184-187 
    Honolulu, June, 2000

  19. A 1GHz POWER4 Testchip Design
  20. B. McCredie, J. Badar, R. Bailey, P. Chou, C. Carter, D. Dreps,. J. Eckhardt, D. Ervin, M. Floyd, A. Haridass, D. Heidel, M. Immediato, J. Keaty, B. Krauter, J. LeBlanc, L. Leitner, D. Malone, D. Mikan, Jr., M. Nealon, J. Petrovick, D. Plass, K. Reick, P. Restle, R. Robertazzi, T. Skergan, K. Stawiasz, H. Stigdon, J. Vargus, J. Warnock, IBM
    Hot Chips 11, Symposium on High-Performance Chips at Stanford University,
    Presentation foils in Conference Proceedings, Palo Alto California, Aug., 1999

  21. A 400 MHz S/390 microprocessor
  22. Webb, C.F. Anderson, C.J. Sigal, L. Shepard, K.L. Liptay, J.S. Warnock, J.D. Curran, B. Krumm, B.W. Mayo, M.D. Camporese, P.J. Schwarz, E.M. Farrell, M.S. Restle, P.J. Averill, R.M., III Slegel, T.J. Houtt, W.V. Chan, Y.H. Wile, B. Nguyen, T.N. Emma, P.G. Beece, D.K. Ching Te Chuang Price, C.
    1997 IEEE international solid-state circuits conference
    San Francisco, California, Digest of Technical Papers, pg. 168, February 1997

  23. A 400 MHz S/390 microprocessor
  24. Webb, C.F. Anderson, C.J. Sigal, L. Shepard, K.L. Liptay, J.S. Warnock, J.D. Curran, B. Krumm, B.W. Mayo, M.D. Camporese, P.J. Schwarz, E.M. Farrell, M.S. Restle, P.J. Averill, R.M., III Slegel, T.J. Houtt, W.V. Chan, Y.H. Wile, B. Nguyen, T.N. Emma, P.G. Beece, D.K. Ching Te Chuang Price, C.
    IEEE Journal of solid state circuits
    Vol. 32, pg. 1665-75, November, 1997

  25. Frequency-Dependent Crosstalk Simulation for On-Chip Interconnections
  26. A. Deutsch, H. H. Smith, C. W. Surovic, G. V. Kopcsay, D. A. Webber, P. W. Coteus, G. A. Katopis, W. D. Becker, A. H. Dansky, G. A. Sai-Halasz, P. J. Restle
    IEEE transactions on advanced packaging
    vol. 22, p. 292-308, August, 1999

  27. When are transmission line effects important for on chip interconnections?
  28. A. Deutsch, G. V. Kopcsay, P. J. Restle, H. H. Smith G. Katopis W. D. Becker, P. W. Coteus, C. W. Surovic, B. J. Rubin, R. P. Dunne, Jr., T. Gallo, K. A. Jenkins, L. M. Terman, R. H. Dennard, G. A. Sai-Halasz, B. L. Krauter, and D. R. Knebel
    IEEE transactions on microwave theory and techniques
    vol. 45, p. 1836-46, October 1997

  29. When are transmission line effects important for on chip interconnections?
  30. A. Deutsch, G. V. Kopcsay, P. J. Restle, H. H. Smith G. Katopis W. D. Becker, P. W. Coteus, C. W. Surovic, B. J. Rubin, R. P. Dunne, Jr., T. Gallo, K. A. Jenkins, L. M. Terman, R. H. Dennard, G. A. Sai-Halasz, B. L. Krauter, and D. R. Knebel
    Proceedings 47th Electronic Components and Technology Conference
    San Jose, California, May 1997

  31. Design guidelines for short, medium, and long on-chip interconnections
  32. A. Deutsch, W. D. Becker, G. A. Katopis, H. Smith, P. J. Restle, P. W. Coteus, C. W. Surovic, G. V. Kopcsay, B. J. Rubin, R. P. Dunne, T. Gallo, K. A. Jenkins, L. M. Terman, R. H. Dennard, D. R. Knebel
    IEEE Topical Meeting on Electrical Performance of Electronic Packaging
    Piscataway, NJ, 1996

  33. Design guidelines for short, medium, and long on-chip interconnections
  34. A. Deutsch et. al.
    Electrical Performance of Electronic Packaging
    Napa, California, Oct. 1996

  35. Optimization of SiGe HBT technology for high speed analog and mixed signal applications
  36. D. L. Harame, J. M. C. Stork, B. S. Meyerson, K. Y. J. Hsu, J. Cotte, K. A. Jenkins, J. D. Cressler, P. Restle, E. F. Crabbe, S. Subbanna, T. E. Tice, B. W. Scharf, J. A. Yasaitis
    IEEE international electron devices meeting
    Technical Digest pg. 71, Washington, DC, Dec. 1993

  37. A new "shift and ratio" method for MOSFET channel-length extraction
  38. Y. Taur, D. S. Zicherman, D. R. Lombardi, P. J. Restle, C. H. Hsu, H. I. Hanafi, M. R. Wordeman, B. Davari, G G. Shahidi
    IEEE electron device letters
    Vol. 13 pg. 267, May, 1992

  39. DRAM variable retention time
  40. P. J. Restle, J. W. Park, B. F. Lloyd
    IEDM International electron devices meeting
    technical digest pg. 807, December, 1992

  41. Design issues for SiGe heterojunction FETs
    S. Verdonckt-Vandebroek, E. F. Crabbe, B. S. Meyerson, D. L. Harame, P. J. Restle, J. M. C. Stork,
    Proc. IEEE Cornell Conf. Adv. Concepts High Speed Semicond. Device Circuit, 1992, p. 425-434

  42. High mobility modulation-doped SiGe-channel p-MOSFETs
  43. E. F. Crabbe, B. S. Meyerson, D. L. Harame, P. J. Restle, J. M. C. Stork, A. C. Megdanis, C. L. Stanis, A. A. Bright G. M. W. Kresen and A. C. Warren
    IEEE Electron Device Letters
    Vol. 12, pg. 447, August, 1991

  44. Graded SiGe-channel modulation-doped p-MOSFETs
    S. Verdonckt-Vandebroek, E. F. Crabbe, B. S. Meyerson, D. L. Harame, P. J. Restle, J. M. C. Stork, A. C. Megdanis, C. L. Stanis, A. A. Bright, G. M. W. Kroesen, A. C. Warren,
    Symposium on VLSI Technology Digest of Technical Papers, Dec. 1991, p. 105-106

  45. Si/SiGe p-channel MOSFETs
    S. Subbanna, V. P. Kesan, M. J. Tejwani, P. J. Restle, D. J. Mis, S. S. Iyer, Symposium on VLSI Technology, Digest of Technical Papers, Dec. 1991, p. 103-104.

  46. Internal probing of submicron FETs and photoemission using individual oxide traps
  47. P. Restle, A. Gnudi
    IBM journal of research and development
    Vol. 34, pg. 227, March/May 1990

  48. Individual oxide traps as probes into submicron devices
  49. P. Restle
    Applied Physics Letters
    Vol. 53, pg. 1862, November, 1988

  50. A 3.5-ns/77K and 6.2-ns/300K 64K CMOS RAM with ECL interfaces
  51. T. I. Chappell, B. A. Chappell, J. W. Allan, J. Y.-C. Sun, S. P. Klepner, R. L. Franch, P. F. Greier, and P. J. Restle
    IEEE journal of solid-state circuits
    Vol. 24, pg. 859, August, 1989

  52. Fast CMOS ECL Recievers with 100-mV worst-case sensitivity
  53. B. A. Chappell, T. I. Chappell, S. E. Schuster, H. M. Segmuller, J. W. Allan, R. L. Franch, P. J. Restle
    IEEE journal of solid-state circuits
    Vol. 23, pg. 59, February 1988

  54. Design and experimental technology for 0.1-micron gate-length low-temperature operation FET's
  55. G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, E. Ganin, S. Rishton, D. S. Zicherman, H. Schmid, M. R. Polcari, H. Y. Hg, P. J. Restle, T. H. P. Chang and R. H. Dennard
    IEEE electron device letters
    Vol. EDL-8, pg. 463, October 1987

  56. Capacitance testing of multi-chip modules for opens and shorts
  57. P. J. Restle, R. E. Schwall, T. J. Bucelot
    IBM Research Report
    RC 16016 (#71185) Engineering Technology, 39 pages, August 1990.

  58. Fabrication of a Metal Carrier (MECA) for packaging applications
  59. P. Madakson, S. Nunes, R. Schwall, H. Yeh, J. Paraszczak, R. Serino, A. Lanzetta, R. McGouey, E. Galligan, J. Cataldo, K. Grebe, P. Restle, W. Graham, H. Tong, E. Miersch
    IBM Research Report
    RC 15283 (#68192) Engineering Technology, 26 pages, December 1989. 

Publications before joining IBM

  1. 1/f noise in semiconductors and metals
  2. Doctoral Thesis
    by Phillip John Restle
    Department of Physics, at University of Illinois at Urbana-Champaign, 1986
     
  3. Noise power studies of the nearly commensurate quasi one-dimensional conductor (NMP)x(Phen)1-x(TCNQ)
  4. H. Rommelmann, A. J. Epstein, J. S. Miller, P. J. Restle, R. D. Black, M. B. Weissman
    Physical Review B Vol. 32, pg. 1257, July 1985
     
  5. Non-Gaussian 1/f noise in small silicon on sapphire samples
  6. P. J. Restle R. J. Hamilton, M. B. Weissman
    Physical Review B Vol. 31, pg. 2254, February 1985
     
  7. Nearly Traceless 1/f Noise in Bismuth
  8. R. D. Black, P. J. Restle, M. B. Weissman
    Phys. Rev. Letters No. Vol. 51(16) 1983
     
  9. Tests of Gaussian statistical properties of 1/f noise
  10. P. J. Restle, M. B. Weissman, R. D. Black,
    J. Appl. Phys. No. 54(10), 1983, p. 5844
     
  11. 1/f noise in Silicon on Sapphire
  12. M. B. Weissman, R. D. Black, P. J. Restle,
    Proceeding of the 7th international conference on noise in physical systems Montpellier, France, May 1983
     
  13. Hall effect, anisotropy, and temperature dependence measurements of 1/f noise in Silicon on Sapphire
  14. R. D. Black, P. J. Restle, M. B. Weissman
    Physical Review B No 28 (1983), pg. 2333.
     
  15. Thermally activated features in 1/f noise in Silicon on Sapphire
  16. M. B. Weissman, R. D. Black, P. J. Restle, T. Ray
    Physical Review B No 27, pg. 1428, January 1983
     
  17. 1/f noise in silicon wafers
  18. R. D. Black, M. B. Weissman, P. J. Restle
    J. Appl. Phy., No 53, 1982, p 6280. 



Phillip Restle restle@us.ibm.com

This page last updated: July 3, 2001