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Name Phillip Restle
Position
Research Staff Member
Group: VLSI Design Systems
Department: VLSI Design
IBM Thomas J.
Watson Research Center
Research Interests
Microprocessor clocking, clock distribution networks,
on-chip
inductance,
interconnect optimization, nonlinear optimization, VLSI design, CAD
tools/Design
Automation.
Contact Information
IBM Thomas J. Watson Research Center
Office 13-225
P.O. Box 218 (or for non-P.O. Box deliveries: Route
134 and Taconic)
Yorktown Heights, NY 10598
U.S.A.
Voice: 914-945-2697, IBM tieline 862-2697
Email (please ignore x's): rxexsxtxlxe@us.ibm.com |
Phillip Restle
Contents
- Patents/Publications Page
- Resonant Clock Page
- Some old invited talks:
- Technical Visualizations in VLSI Design
by Phillip Restle, Design Automation Conference, Invited Talk,
Technical Digest pg. 494, Las Vegas, California, June 21, 2001.
PDF
file
Higher resolution controllable
animations
from talk (and more)
Including:
- Simple Lines and Wireframe figures
- 3D Surface Plots
- 3D visualizations with Z=Delay
- Voltage & Current visualizations of full-wave
interconnect
analysis
- Clock Distributions 500 MHz to 4 GHz
- Circuit-tuning animations
- Multi-GHz Clock
Networks
Click here to see slides and subset
of animations
Phillip J. Restle,
IEEE SSCTC Workshop on Design for Multi-GigaHertz
Processors,
San Fransico, Feb. 7, 2000
Education
Employment
| 1986-present |
Research Staff Member |
IBM Thomas J. Watson Research Center |
| 1980-1982 |
Teaching Assistant |
University of Illinois physics department |
| 1979-1980 |
Research Assistant |
University of Illinois nuclear physics lab |
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