The official
corporate bio for Dr. Gschwind is hosted by the IBM Research
Communications team.
Dr. Gschwind's research focuses on the design and implementation of
novel high-performance architectures exploiting parallelism at all
levels, and their compiler and tools support. Recognizing the
importance of his vision for exploiting parallelism at multiple levels
to drive the design of future computing systems, Dr. Gschwind was
honored by InformationWeek as an IT
Innovator and Influencer.
Dr. Gschwind was one of the lead architects for the Cell Broadband
Engine, having contributed to the definition of both the Cell
Synergistic Processor Element, and the Cell system architecture with
coherent DMA from a shared system memory address space. In the course
of the project, Dr. Gschwind served as a technical leader for
architecture definition and as a member of the inter-company technical
company team representing IBM (jointly with Jim Kahle, Chuck Moore,
Marty Hopkins, Peter Hofstee). Dr. Gschwind also developed the first
Cell BE compiler targeting the SPE to demonstrate key optimization
techniques, and helped define the ABIs, integrated executable
strategy, libraries and programming environment for the Cell BE.
Dr. Gschwind has contributed to numerous IBM products as design lead
and member of the technical leadership team for several next
generation microprocessors, as the leader for architecture definition
for several IBM SIMD programming extensions (including extensions to
the VMX instruction set in several OEM systems), as architecture lead
for the IBM PERCS project, and the evaluation of future
microarchitectures for the IBM Power Architecture and mainframe
systems.
In addition to his contributions to future IBM products, Dr. Gschwind
served as a technical leader for IBM's dynamic compilation and very
long instruction word architecture projects, and for the evaluation of
power/performance efficiency as a leader of the low FO4
architecture project and working with the power-aware microarchitecture team.
Dr. Gschwind's contributions to IBM's technology leadership have been
recognized with the honorary title of IBM Master Inventor and his
contributions to several projects have been classified as Research
Division Accomplishments. Dr. Gschwind is the recipient of 20 IBM
Invention Plateaus, an IBM Best Research Paper award, and a variety of
other corporate awards in recognition to IBM's technical and business
success.
Dr. Gschwind is the Chairman of the IBM Research Computer Architecture
Professional Interest Community, and has served on the program and
organizing committees of many major conferences, and is currently
Program Co-Chair for the ACM
Computing Frontiers 2008, jointly with Prof. Gianfranco Bilardi of
the Universita di Padova, and a program committee member for PACT
2007, IISWC 2007, dasCMP 2007, MuCoCos 2008 and ISPASS 2008.
Dr. Gschwind was the keynote speaker at the ACM Computing Frontiers 2006
conference, and will deliver the keynote speeches at the PACT 2007
Workshop on Operating System support for Heterogeneous Multicore
Architectures, and the First
Workshop on General Purpose Processing on Graphics Processing
Units.
In addition to his corporate contributions, Dr. Gschwind has taught
ELE475: Advanced Computer Architecture at the Electrical Engineering Department of
Princeton University.
Before joining IBM, Dr. Gschwind was Assistant Professor at Technische
Universität Wien in Vienna, Austria where he conducted research
on application specific processors, CAD support for architecture
evaluation and implementation, FPGA-based rapid prototyping of
microprocessors, and compilation techniques.
Dr. Gschwind is a Fellow of the IEEE in recognition of his contributions
to high-performance computer architecture and compilation technology
and has Erdös number 3.
- Cell Broadband Engine - Enabling Density Computing for Data-Rich Environments
- ISCA 2006 Tutorial, Boston, MA, June 2006.
- Chip Multiprocessing and the Cell Broadband Engine
- ACM Computing Frontiers 2006 Keynote, Ischia, Italy, May 2006.
- Dynamic Compilation at the System Level
- CGO 2006 Tutorial, New York, May 2006.
- A
Novel SIMD Architecture for the Cell Heterogeneous Chip Multiprocessor
- Hot Chips 17, Palo Alto, CA, August 2005.
- Cell GC: Using the Cell
Synergistic Processor as a Garbage Collection Coprocessor [slides]
- ACM Conference on Virtual Execution Environments VEE 2008,
Seattle, WA, March 2008. (with C.-Y. Cher)
- An Open Source Environment for Cell Broadband Engine System Software
- IEEE Computer, June 2007. (with D. Erb, S. Manning, M. Nutter)
- The
Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a
Chip Multiprocessor
- International Journal of Parallel Programming, June 2007. [Springer]
- Chip
Multiprocessing and the Cell Broadband Engine
- ACM Computing Frontiers 2006, May 2006.
- Synergistic Processing in Cell's Multicore Architecture
- IEEE Micro, March 2006. (M. Gschwind,
P. Hofstee, B. Flachs, M. Hopkins, Y. Watanabe, T. Yamazaki)
- A compiler enabling and
exploiting the Cell broadband processor architecture
- IBM Systems Journal Special Issue on Online Game Technology,
Volume 45, Number 1, January 2006. (with A. E. Eichenberger,
J. K. O'Brien, K. M. O'Brien, P. Wu ,T. Chen, P. H. Oden,
D. A. Prener, J. C. Shepherd, B. So, Z. Sura, A. Wang, T. Zhang, P.
Zhao, M. K. Gschwind, R. Archambault, Y. Gao, R. Koo)
- Optimizing
Compiler for the Cell Processor
- PACT 2005, September 2005. (with A. Eichenberger, K. O'Brien,
K. O'Brien, P. Wu, T. Chen, P. Oden D. Prener, J, Shepherd, B. So,
Z. Sura, A Wang, T. Zhang, P. Zhao))
- Power and Performance Optimization at the
System Level
- Computing Frontiers 2005, May 2005. (with V. Salapura et al.)
- Exploring realtime multimedia content creation in video games
- 6th Workshop on Media and Streaming Processors in conjunction with
MICRO 36, December 2004. (with B. Matthews, J.D. Wellman)
- Integrated
Analysis of Power and Performance for Pipelined Microprocessors
- IEEE Transactions on Computers, Vol. 53, No. 8, August 2004. (with
V. Zyuban, D. Brooks, V. Srinivasan, P. Bose, P. Emma, P. Strenski)
- Optimizing Pipelines for Power and Performance
- ACM/IEEE 35th International Symposium on Microarchitecture, Istanbul,
Turkey, November 2002. (with V. Srinivasan, D. Brooks,
P. Bose, P. Emma, V. Zyuban, P. Strenski) Best IBM Research Paper 2002
- Precise Exceptions in Dynamic Optimization
- Proc. 2002 Symposium on Compiler Construction, (CC 2002), Grenoble,
France, April 2002. (with E.R. Altman)
- Dynamic Binary Translation and Optimization
- IEEE Transactions on Computers -- Special Issue on Dynamic
Optimization, June 2001. (with K. Ebcioglu, E. Altman,
S. Sathaye)
- Advances and Future Challenges in Dynamic Compilation
- Proceedings of the IEEE, November 2001.
(with K. Ebcioglu, E. Altman, S. Sathaye)
- FPGA Prototyping of a RISC Processor
Core for Embedded Applications
- IEEE Transactions on VLSI, April 2001. (with V. Salapura,
D. Maurer)
- Binary Translation and Architecture
Convergence Issues for IBM System/390
- International Conference on Supercomputing 2000, Santa Fe, NM,
May 2000.
(with K. Ebcioglu, E. Altman, S. Sathaye)
- Dynamic
and Transparent Binary Translation
- IEEE Computer, March 2000.
(with E. Altman, S. Sathaye, P. Ledak, D. Appenzeller)
- BOA: Targeting Multi-Gigahertz with Binary Translation
- 1999 Workshop on Binary Translation in conjunction with PACT '99, Newport Beach, CA, October 1999.
IEEE Computer Society Technical Committe on Computer Architecture
Newsletter, December 1999.
(with S. Sathaye, P. Ledak, J. LeBlanc, S. Kosonocky,
J. Fritts, Z. Filan, A. Bright, D. Appenzeller, E. Altman,
C. Agricola) Best Paper Award
- Instruction Set Selection for ASIP Design
- ACM Seventh International Workshop on Hardware/Software Co-Design,
Rome, Italy, May 1999.
- Method and apparatus for creating and executing integrated executables
in a heterogeneous architecture
-
M. Gschwind, K. O'Brien, K. O'Brien, V. Salapura
07/10/2007 Issued as US Patent 7243333
- Method and apparatus for overlay management within an
integrated executable for a heterogeneous architecture
-
M. Gschwind, K. O'Brien, K. O'Brien, V. Salapura
05/22/2007 Issued as US Patent 7222332
- Method and apparatus for mapping debugging information when
debugging integrated executables in a heterogeneous architecture
-
M. Gschwind, K. O'Brien, K. O'Brien, V. Salapura
05/01/2007 Issued as US patent 7213123
- Method and apparatus for enabling access to global data by
a plurality of codes in an integrated executable for a heterogeneous
architecture
-
M. Gschwind, K. O'Brien, K. O'Brien, V. Salapura
04/03/2007 Issued as US patent 7200840
- Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions
-
E. Altman, P. Capek, M. Gschwind, P. Hofstee, J.
Kahle, R. Nair, S. Sathaye, J. Wellman
11/29/2005 Issued as US patent 6970982
- Method
and apparatus for software-assisted thermal management for electronic systems
-
M. Gschwind, V. Salapura
9/20/2005 Issued as US patent 6948082 Top 10% licensing award
- Symmetric multiprocessing system utilizing a DMAC to allow address translation
- E. Altman, P. Capek, M. Gschwind, P. Hofstee, J.
Kahle, R. Nair, S. Sathaye, J. Wellman
6/14/2005 Issued as US patent 6907477
- SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode
-
M. Gschwind, P. Hofstee, M. Hopkins
1/4/2005 Issued as US patent 6839828 Top 10% licensing award
- Symmetric
multi-processing system with attached processing units being able to
access a shared memory without being structurally configured with an
address translation mechanism
-
E. Altman, P. Capek, M. Gschwind, P. Hofstee, J. Kahle, R. Nair,
S. Sathaye, J. Wellman, M. Suzuoki, T. Yamazaki
8/17/2004 Issued as US patent 6779049 Top 10% licensing award
-
Method and apparatus for implementing execution predicates in a computer processing system
-
M. Gschwind, S. Sathaye
1/28/2003 Issued as US patent 6513109 Top 10% licensing award
-
Methods and apparatus for reordering and renaming memory references in a multiprocessor computer system
-
E. Altman, K. Ebcioglu, M. Gschwind, S. Sathaye
02/19/2002 Issued as US patent 6349361
-
Pipeline control for high-frequency pipelined designs
-
M.K. Gschwind
02/20/2000 Issued as US patent 6192466 Top 10% licensing award
IEEE
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by Association for Computing Machinery, Inc. Permission to make
digital or hard copies of part of all of this work for personal or
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otherwise, to republish, to post on servers, or to redistribute to
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![[Michael Gschwind]](Images/mkg.jpg)
Michael Gschwind
IBM Master Inventor
IBM T.J. Watson Research Center
Route 134
Yorktown Heights, NY 10598-0218
mikeg AT
watson DOT ibm DOT com
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