Our dynamic compilation system collects and exploits runtime system information to dynamically reoptimize code for specific workload behavior for both user and system code. In addition, many traditional static optimization techniques are employed, but with an extreme bias towards execution speed as opposed to code quality. Nevertheless code quality is generally close that that of static optimizers. Among the optimizations performed are global scheduling, loop unrolling, loop peeling, superblock formation, and constant propagation. Alias analysis is also done, but unlike traditional static compilers, a conservative approach is not needed -- if in doubt, rescheduling is allowed.

The dynamic runtime optimization system operates on a simple static architecture designed to achieve high ILP and high frequency. We believe that this combination of raw execution speed and high-level code adaptation is an attractive way to build future architectures. While dynamic compilation and code optimization techniques described in this talk can be used to optimize code for native PowerPC execution, we believe that even greater benefits can be obtained by combining the runtime environment with a specially designed architecture, which provides additional capabilities such as additional rename registers and hardware support for exception recovery. In addition to these optimization advantages, the virtualization layer introduced by the dynamic compilation system offers the ability to customize the underlying execution engine and completely redefine the hardware interface, while maintaining binary compatibility at the software level (at either the program or operating system level, depending on the implementation choices made).

In addition, the increasing number of threads becoming available due to SMT and CMP systems, make dynamic translation and optimization ever more attractive, as translation and optimization time, need not come at the direct expense of executing applications. Dynamic translation and optimization have other properties that are especially desirable now: As processors become more complex to develop, dynamic translation and optimization has the potential to allow a single core to efficiently execute code for multiple ISA's. In addition, as existing software increasingly limits the ability to introduce or change ISA's, dynamic translation and optimization offer the opportunity to introduce new architecture and new features "under the covers".

IBM first introduced the techniques to dynamically optimize code with the DAISY system in 1996, and since then, a number of dynamic compilation systems based on this technology have expanded possible uses, such as the IBM BOA project, the University of Wisconsin's Co-Designed Virtual Machines project, Transmeta's Crusoe processor technology, HP's Dynamo dynamic optimization system, and the Itanium-based Aries and IA32-EL execution layers. There is also a signficant overlap between these technologies and the numerous Java JITs that have been developed.

In this talk, the authors will describe

• the basic DAISY system technology,
• elements of high ILP and high frequency design in BOA,
• advanced optimization technologies for use in dynamic compilation systems,
• performance evaluation, and evaluation of the impact of a number of system and compilation parameters,
• a discussion of challenges in booting an unmodified operating system on a dynamic compilation layer,
• and a comparison of dynamic compilation systems

We close with an outlook on possible future application areas for this technology.

The tutorial is aimed at researchers and practitioners in the field of compilation and dynamic runtime environments, and specifically dynamic compilation, continuous program optimization, and just-in-time compilation, as well as related disciplines such as computer architecture. Attendees will learn the impact of a number of decisions in the design of a full system dynamic optimization approach, and challenges in providing a transparent interface to execute operating systems unmodified. Using these technologies, researchers will be able to perform continuous on-line program optimizations based on dynamic compilation techniques programs to take maximum advantage of hardware resources available. In recent years, several efforts based on this technology have been announced and introduced.

Presenters

Dr. Gschwind is an architect for the IBM Power Architecture, and a logic design lead for a future IBM system. Previously, he provided technical leadership for the BOA project through his contributions on high-performance, high-frequency architecture design, and advanced dynamic compilation techniques. Since the completion of the BOA project, Dr. Gschwind has held key technical positions in a variety of computer architecture projects. Dr. Gschwind was one of the initiators of the media processor development project which led to the creation of the CELL processor jointly with SONY and Toshiba and is currently being designed by the Sony/Toshiba/IBM STI alliance in Austin, Texas. Dr. Gschwind provided key architecture and compilation technology to the CELL project. Dr. Gschwind is the author of numerous papers and holds patents on dynamic compilation, VLIW architecture, media processing technology, and computer microarchitecture.

Dr. Altman was one of the initiators of the original DAISY concept which introduced dynamically architected instruction sets to the world. Before his work on DAISY, Dr. Altman conducted research in advanced compilation techniques and VLIW processor architecture. Since the release of the DAISY system. Dr. Altman has provided leadership in the design of the second generation BOA systems, and has contributed to a variety of microarchitecture and architecture projects at IBM. In 2000, Dr. Altman was a key contributer to the collaborative media processor development with SONY and Toshiba corporations, which later became know as CELL. Dr. Altman is the author of numerous papers and holds patents on dynamic compilation, VLIW architecture, and media processing technology, and computer microarchitecture.