PUBLICATIONS

Ph.D. Thesis: "STRiP, A Self-Timed RISC Processor Architecture."

By using: (1) a self-timed pipeline sequencing method called dynamic clocking, (2) a zero-level cache with predictive prefetching, and (3) an asynchronous external interfaces, a 32-bit RISC processor is developed which requires no external clocks, provides approximately twice the performance of an equivalent synchronous design and whose operating frequency adapts to the system's environmental conditions. STRiP's sequencing structure and asynchronous external interface eliminates synchronization and meta-stability problems normally encountered when interfacing devices with different operating rates. The dynamic clocking sequencing method also removes the need for dual-rail encoding and completion signaling between functional units (required by other self-timed design styles).

Conference Papers

M. E. Dean, D. L. Dill, and M. Horowitz. "Self-Timed Logic Using Current-Sensing Completion Detection (CSCD)." Journal of VLSI Signal Processing, Kluwer Academic Publishers, July 1994.

M. E. Dean, D. L. Dill, and M. Horowitz. "Self-timed Logic Using Current Sensing Completion Detection (CSCD)." IEEE International Conference on Computer Design: VLSI in Computers & Processors, ICCD-1991. IEEE Computer Society Press, October 1991, pp. 187-191.

M. E. Dean, T. E. Williams, and D. L. Dill. "Efficient Self-timing with Level-Encoded Two-Phase Dual-Rail (LEDR)." Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, MIT Press, March 1991, pp. 55-70.

Patents

M. E. Dean, D. Glasco, G. D. Carpenter, "Non-Uniform Memory Access (NUMA) Data Processing System that Speculatively Issues Requests on a Node Interconnect." Issued May 23, 2000, U.S. Patent No. 6067603.


M. E. Dean, D. Glasco, R. N. Iachetta, G. D. Carpenter, "Non-Uniform Memory Access (NUMA) Data Processing System that Buffers Potential Third Node Transactions to Decrease Communication Latency." Issued May 23, 2000, U.S. Patent No. 6067611.

M. E. Dean, D. Glasco, R. N. Iachetta, G. D. Carpenter, "Non-Uniform Memory Access (NUMA) Data Processing System that Speculatively Issues Requests on a Node Interconnect." Issued June 27, 2000, U.S. Patent No. 6081874.

M. E. Dean, D. Glasco, G. D. Carpenter, "Non-Uniform Memory Access (NUMA) Data Processing System that Permits Multiple Caches to Concurrently Hold Data in a Recent State from which Data can be Sourced by Shared Intervention." Issued September 5, 2000, U.S. Patent No. 6115804.

M. E. Dean, D. Glasco, R. L. Rockhold, P. L. De Backer "Interrupt Architecture for a Non-Uniform Memory Access (NUMA) Data Processing System." Issued November 14, 2000, U.S. Patent No. 6148361.

M. E. Dean, W. G. Voigt, G. D. Carpenter, D. P. Beaman. "Method and System for Interfacing an Upgrade Processor to a Data Processing System." Issued April, 1999, U.S. Patent No. 5,898,857.

M. E. Dean, Thoi Nguyen. "Bus Interface Logic Unit." Issued June, 1998, U.S. Patent No. 5,768,550.

M. E. Dean, G. D. Carpenter. "Method and System for Reading from a M-Byte Memory Utilizing a Processor Having a N-Byte Data Bus. " Issued February, 1997, U.S. Patent No. 5,603,041.

M. E. Dean. "Method for Dynamically Sequencing Operation of a Self-Timed Processing System." Issued September, 1996, U.S. Patent No. 5,553,276.

M. E. Dean. "System and Method for Prefetching Information in a Processing System." Issued August, 1996, U.S. Patent No. 5,544,342.

M. E. Dean, M. R. Faucher, J. C. Peterson, H. C. Tanner, G. D. Carpenter. "Non-Contiguous Mapping of I/O Addresses to use Page Protection of a Processor. " Issued August, 1996, U.S. Patent No. 5,548,746.

M. E. Dean, M. R. Faucher, J. C. Peterson, H. C. Tanner, S. E. Curry. "Connecting A Short Word Length Non-Volatile Memory to a Long Word Length Address/Data Multiplexed Bus. " Issued September, 1995, US. Patent No. 5,448,521.

R. M. Begun, P. M. Bland, and M. E. Dean. "Microcomputer System Employing Address Offset Mechanism to Increase the Supported Cache Memory Capacity." Issued September, 1995, U.S. Patent No. 5,450,559.

R. M. Begun, P. M. Bland, and M. E. Dean. "Method and Apparatus for Selectively Posting Write Cycles Using the 82385 Cache Controller." Issued July, 1994, U.S. Patent No. 5,327,545.

R. M. Begun, P. M. Bland, and M. E. Dean. "Microprocessor Hold and Lock Circuitry." Issued December, 1992, U.S. Patent No. 5170481.

R. M. Begun, P. M. Bland, and M. E. Dean. "Delayed Cache Write Enable Circuit for a Dual Bus Microcormputer System with an 80386 and 82385." Issued December, 1992, U.S. Patent No. 5175826.

P. M. Bland and M. E. Dean. "System Bus Preempt for 80386 when Running in an 80386/82385 Microcomputer System with Arbitration." Issued July, 1992, U.S. Patent No. 5,129,090.

R. M. Begun, P. M. Bland, and M. E. Dean. "Control of Pipelined Operation in a Microcomputer System Employing Dynamic Bus Sizing with 80386 Processor and 82385 Cache Controller." Issued June, 1992, U.S. Patent No. 5,125,084.

M. Bland, M. E. Dean, G. J. Gaudenzi, K. G. Kramer, and S. L. Tempest. "Bidirectional Buffer with Latch and Parity Capability." Issued April, 1992, U.S. Patent No. 5,107,507.

R. M. Begun, P. M. Bland, and M. E. Dean. "Method and Apparatus for Selectively Posting Write Cycles Using the 82385 Cache Controller." Issued September, 1991, U.S. Patent No. 5,045,998.

M. E. Dean, et al. "Apparatus and Method for Accessing Data Stored in a Page Mode Memory." Issued July, 1991, U.S. Patent No. 5,034,917.

M. E. Dean and D. L. Moeller. "Data Processing System Including a Main Processor and Co-processor and Co-processor Error Handling Logic." Issued July, 1986, U.S. Patent No. 4,598,356.

M. E. Dean. "Refresh Generator System for a Dynamic Memory." Issued March, 1986, U.S. Patent No. 4,575,826.

M. E. Dean and D. L. Moeller. "Microcomputer System with Bus Control Means for Peripheral Processing Devices." Issued July, 1985, U.S. Patent No. 4,528,626.

M. E. Dean, L. C. Eggebrecht, D. A. Kummer, and J. A. Saenz. "Color Video Display System Having Programmable Border Color." Issued March, 1984, U.S. Patent No. 4,437,092.

M. E. Dean, D. A. Kummer, and J. A. Saenz. "Composite Video Color Signal Generation from Digital Color Signals." Issued April, 1984, U.S. Patent No. 4,442,428.

IBM Technical Disclosures and Publications

M. E. Dean, M. R. Faucher, J. C. Peterson, H. Q. Bui, H. C. Tanner, S. E. Curry. "Sandalfoot Memory Map." IBM Technical Disclosure Bulletin (May 1995).

M. E. Dean, B. J. Wolford, J. C. Peterson, H. Q. Bui, H. C. Tanner, S. E. Curry. "Box Bus to PCI Bridge." IBM Technical Disclosure Bulletin (May 1995).

M. E. Dean, M. R. Faucher, J. C. Peterson, H. C. Tanner, S. E. Curry. "Memory Mapped PCI Configuration Cycles." IBM Technical Disclosure Bulletin (May 1995).

M. E. Dean, B. J. Wolford, J. C. Peterson, H. Q. Bui, S. E. Curry. "Arbitration for a PowerPC CPU Bus/PCI Bus System." IBM Technical Disclosure Bulletin (May 1995).

M. E. Dean, J. C. Peterson, S. E. Curry. "Protocol for Asynchronous System Error Reporting in a PowerPC System." IBM Technical Disclosure Bulletin (May 1995).

M. E. Dean, J. C. Peterson, H. C. Tanner. "Means to Utilize PCI Level Sensitive Interrupts Within a FSA-PC Edge Sensitive Environment." IBM Technical Disclosure Bulletin (May 1995).

M. E. Dean, J. M. Stafford, G. D. Carpenter. "Switching of a PowerPC 601 System From Big Endian to Little Endian." IBM Technical Disclosure Bulletin (March 1995).

M. E. Dean, J. C. Peterson, H. Q. Bui, S. E. Curry. "60X/PCS Bus Memory Controller Design with Cache Coherency." IBM Technical Disclosure Bulletin (March 1995).

M. E. Dean, M. R. Faucher, J. C. Peterson, H. Q. Bui, H. C. Tanner, S. E. Curry, G. D. Carpenter. "Bi-Endian Support Hardware in a PowerPC System." IBM Technical Disclosure Bulletin (March 1995).

M. E. Dean, M. R. Faucher, J. C. Peterson, H. C. Tanner, S. E. Curry. "Memory Mapped Interrupt Acknowledge on PowerPC." IBM Technical Disclosure Bulletin (January 1995).

M. E. Dean, A. M. Lyford, and J. D. Reid. "Multiple Bus Master with Arbitration and Preempt Capability for Personal Computers." IBM Technical Disclosure Bulletin (September 1991), pp. 16-18.

M. E. Dean, B. C. Drerup, J. C. Peterson, and W. G. Voigt. "Micro Channel Planar to Adapter Card Interrupt Redirection." IBM Technical Disclosure Bulletin (August 1991), pp. 392-393.

M. E. Dean, R. Davila, K. M. Zyvoloski, and R. M. Begun. "Method for Downloading Firmware to Ram." IBM Technical Disclosure Bulletin (December 1990), pp. 342-346.

M. E. Dean, R. Davila, and K. M. Zyvoloski. "System Debug Facility - A System Testing Computer Architecture for High-Speed Processing Systems." IBM Technical Disclosure Bulletin (December 1990), pp. 123-128.

M. E. Dean and J. D. Taylo. "External Burst-Mode FIFO for Non-Burst Diskette Controller." IBM Technical Disclosure Bulletin (August 1990), pp. 299-301.

M. E. Dean, R. M. Begun, P. M. Bland, and P. E. Milling. "Bus-Locking Mechanism in an Intel 82385 Cache Controller Subsystem." IBM Technical Disclosure Bulletin (November 1989), pp. 208-210.

M. E. Dean and R. M. Begun. "Intel 82385 Snoop Diagnostic Circuit to Test DMA/Bus Master Snoop Cycles." IBM Technical Disclosure Bulletin (October 1989), pp. 126-128.

M.E. Dean, R. M. Begun, and P. E. Milling. "Support Circuit for Intel 80386/82385 System with optional Intel 80387." IBM Technical Disclosure Bulletin (October 1989), pp. 84-86.

R. Bealkowski, R. Davila, M. E. Dean, C. T. Lehman, and K. M. Zyvoloski. "Preventing Unauthorized Access on a Personal Computer System." IBM Technical Disclosure Bulletin (September 1989), pp. 125-128.

R. Bealkowski, M. E. Dean, D. E. Judice, and K. M. Jackson. "Event Latching in an Asynchronous Environment." IBM Technical Disclosure Bulletin (September 1989), pp. 196-197.

R. M. Begun, M. E. Dean, and T. H. Davis. "Planar/Processor Interface for Personal Systems." IBM Technical Disclosure Bulletin (August 1989), pp. 187-189.

M. E. Dean. "Integrated Input/Output Support Circuitry for use with 80286/80386 Microprocessors." IBM Technical Disclosure Bulletin (July 1989), pp. 205-216.
M. E. Dean, R. Davila, K. M. Zyvoloski, and R. M. Begun. "Microprocessor Bus State Monitor System." IBM Technical Disclosure Bulletin (February 1989), pp. 399-404.

C. A. Heath, M. E. Dean, D. M. Desai, J. Nicholson, J. Reid, M. R. Turner, and F. Strietelmeier. "Bus Data Transfer Controls for Personal Computers." IBM Technical Disclosure Bulletin (December 1987), pp. 455-456.

M. E. Dean, K. A. Hausman, C. A. Heath, and K. M. Jackson. "Diagnostic Status for Non-Maskable Interrupt Arbitration." IBM Technical Disclosure Bulletin (October 1987), pp. 67-68.

M. E. Dean, K. M. Jackson, and K. A. Hausman. "Interrupt Arbitration to Prevent Data Overrun." IBM Technical Disclosure Bulletin (October 1987), pp. 50-51.

C. A. Heath, M. E. Dean, K. A. Hausman, and K. M. Jackson. "Interrupt Arbitration in Personal Computer Systems." IBM Technical Disclosure Bulletin (September 1987), pp. 1785.

M. E. Dean, R. Baker, and D. Kummer. "Composite Video Color Signal Generator." IBM Technical Disclosure Bulletin (January 1985), pp. 4821-4823.

M. E. Dean, D. A. Kummer, and J. A. Saenz. "Page Mode Operation of Dynamic Graphics Memory." IBM Technical Disclosure Bulletin (December 1984), pp. 3876-3877.

M. E. Dean and T. H. Davis. "Memory Decode Architecture." IBM Technical Disclosure Bulletin (September 1984), pp. 2290-2291.

D. Moeller and M. E. Dean. "Keyboard Controller." IBM Technical Disclosure Bulletin (August 1984), pp. 1705.

M. E. Dean and D. Moeller. "16-bit Data Transfer Using 8-bit Direct-Memory Access Controller." IBM Technical Disclosure Bulletin (August 1984), pp. 1699-1700.

M. E. Dean and D. Moeller. "Wait-State Generator." IBM Technical Disclosure Bulletin (August 1984), pp. 1695-1696.

M. E. Dean. "Processor Shutdown Circuit." IBM Technical Disclosure Bulletin (August 1984), pp. 1691.

M. E. Dean, D. A. Kummer, and J. A. Saenz. "CPU Handshake to a Dual-Ported Graphics Memory." IBM Technical Disclosure Bulletin (August 1984), pp. 1655-1657.

M. E. Dean, L. C. Eggebrecht, D. A. Kummer, and J. A. Saenz. "CRT Controller with Increased Addressing Capability." IBM Technical Disclosure Bulletin (September 1982), pp. 2206-2207.

C. Eggebrecht, J. A. Saenz, M. E. Dean, and S. W. Trynosky. "Dot Insert Logic for Graphic Characters." IBM Technical Disclosure Bulletin (September 1982), pp. 2204-2205.

M. E. Dean, J. A. Saenz, D. A. Kummer, and L. C. Eggebrecht. "Palette Select Scheme for a Color Graphics Display." IBM Technical Disclosure Bulletin (September 1982), pp. 2201-2203.