Pradip Bose's External (non-IBM) Home Page

Pradip Bose

Publications in refereed conferences and journals

B. R. Rau and P. Bose, "Directly Interpretable Language Design for High Level Language Support," Proc. Int'l. Wkshp. on High-Level Lang. Comp. Arch. Ft. Lauderdale, May 1980, pp. 52-63.
P. Bose, B. R. Rau and M. S. Schlansker, "Systematically Derived Instruction Sets for High-Level Language Support," Proc. 20th Ann. ACM Southeast Reg. Conf. Knoxville, April 1982, pp 73-84.
P. Bose and J. A. Abraham, "Test Generation for Programmable Logic Arrays," Proc. 19th ACM/IEEE Design Automation Conf. Las Vegas, Nevada, June 1982, pp. 574-580; also appears as a Book Chapter in: Test Generation for VLSI Chips, V. D. Agrawal and S. C. Seth, ed., IEEE Computer Society Press, 1988.
P. Bose, B. R. Rau, M. S. Schlansker and E. S. Davidson, "Syntax- and Semantics-Directed Design and Encoding of HLL-Oriented Instruction Sets," Proc. Int'l. Wkshp. on High-Level Lang. Comp. Arch. Ft. Lauderdale, December 1982, pp. 242-250.
P. Bose and E. S. Davidson, "Design of Instruction Sets for Efficient Support of High-Level Languages," Proc. Int'l. Wkshp. on High-Level Lang. Comp. Arch. Los Angeles, May 1984, pp. 7.10-7.19.
P. Bose and E. S. Davidson, "Design of Instruction Set Architectures for Support of High-Level Languages," Proc. 11th Ann. Int'l. Symp. on Computer Arch. Ann Arbor, Michigan, June 1984, pp. 198-206; IEEE, 711-4/0000/0198, 1984.
P. Bose, "Generation of Minimal and Near-Minimal Test Sets for Programmable Logic Arrays," Proc. IEEE Int'l. Conf. on Computers, Systems and Signal Processing Bangalore, India, December 1984, pp. 702-706.
P. Bose, "Logical Fault Analysis and Design for Testability of Programmable Logic Arrays," Proc. 23rd. Ann. Allerton Conf. Monticello, Illinois, pp. 158-167, October 1985.
P. Bose, "Optimal Code Generation Algorithms for Arithmetic Expressions Executing on Pipelined, Decoupled Architectures," Proc. IEEE International Conference on Computer Design Rye, NY, October 1986, pp. 43-47.
P. Bose, "Optimal Code Generation for Expressions on Super Scalar Machines," Proc. Fall Joint Computer Conference Dallas, November 1986, pp. 372-379.
P. Bose, "DEPLOMAT: a Design Expert for PLa Optimization, MAintenance and Test," Proc. 4th Annual Conf. on Intelligent Systems and Machines Rochester, MI, April 1986, pp. 37-42. (Updated version in Proc. IEEE International Conference on Computer Design Rye, NY, October 1987), July 1987.
P. Bose, "Heuristic, Rule-Based Program Transformations for Enhanced Vectorization," Proc. 1988 ACM Int'l. Conf. on Parallel Processing St. Charles, Illinois, August '88.
P. Bose, "Heuristics-Directed Test Generation for Programmable Logic Arrays," Workshop Digest, 1988 IEEE VLSI Test Workshop Atlantic City, NJ, pp. March 22-23, 1988.
P. Bose, "Parallel Simulation and Test of VLSI Array Logic," Proc. AEGIAN Workshop on Computing (AWOC 88): 3rd. Int'l. Wkshp. on Parallel Computation and VLSI Theory June 28 - July 1, 1988; also appeared as a Springer-Verlag Lecture Note Series publication (Book Chapter) , 1988.
P. Bose, "Interactive Program Improvement Via EAVE: an Expert Adviser for Vectorization," Proc. ACM 1988 Int'l Conf. on Supercomputing Saint Malo, France, July '88.
P. Bose, "Parallel logic/fault simulation for VLSI array logic," Proc. Int'l. Conf. on Computer-Aided Design (ICCAD) November 1988.
P. Bose, A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem," IEEE Trans. on Computers Vol. 37, No. 12, December 1988.
P. Bose, "Matricized fault simulation and test generation for efficient parallel processing," Proc. 1989 IEEE VLSI Test Workshop April 1989.
P. Bose, "Expert CAD techniques for VLSI logic," Proc. Prof. A. K. Chaudhury Commemoration Symposium on Circuits, Systems and Computers Calcutta, India, February 1990.
S. Chaudhury, P. Bose and A. Sengupta, "Connectivity verification of printed circuit boards: a fast AI approach," Book Chapter (pp. 155-163) in Frontiers in Knowledge-Based Computing, eds. V. P. Bhatkar and K. M. Rege, Narosa Publishing House, India 1991. Revised version of paper which appeared earlier in: Proc. KBCS-90 (Knowledge-Based Computer Systems) conference Pune, India, December 1990.
P. Bose, "Early performance estimation of super scalar machine models," Proc. IEEE Int'l. Conf. on Computer Design Cambridge, MA, October 1991, pp. 388-392.
P. Bose, D. LaPotin and G. Vijayan, "Workload-driven floorplanning for MIPS optimization," Proc. IEEE Int'l. Conf. on Computer Design (ICCD) Oct. 1992. .sp
P. Bose and J-D Wellman, "MIPS-driven early design and analysis of VLSI CPU chips," Proc. IEEE VLSI Design-93 Bombay, Jan. 1993.
P. Bose, "Architectural timing verification and test for super scalar processors," Proc. 24th. Ann. Int'l. Symp. on Fault-Tolerant Computing, FTCS-24 Austin, TX, pp. 256-265, June 1994.
S. Surya, P. Bose and J. A. Abraham, "Architectural timing model validation: PowerPC processor family," Proc. IEEE Int'l. Conf. on Computer Design (ICCD) Cambridge, MA, June 1994.
P. Bose and S. Surya, "Architectural timing verification of CMOS RISC processors," IBM J. Res. & Development Vol. 39, No. 1/2, pp. 113-129, Jan/Mar 1995.
V. Iyengar, L. H. Trevillyan and P. Bose, "Representative traces for processor models with infinite cache," Proc. 2nd. Symposium on High Performance Computer Architecture (HPCA-2) , Feb. 1996.
A-T. Nguyen, P. Bose and J-D. Wellman, "PARSIM: a parallel trace-driven simulation facility for fast and accurate performance analysis studies," Proc. IEEE Int'l. Performance, Computing and Communication Conference (IPCCC) , Feb. 1997.
A-T. Nguyen, P. Bose, K. Ekanadham, A. Nanda and M. Michael, "Accuracy and speed-up of parallel trace-driven architectural simulation," Proc. IEEE Int'l. Parallel Processing Symposium , Geneva, March 1997.

Refereed and/or Invited Conference Presentations (without archival proceedings): selected talks

P. Bose, "Area Efficient Realization of Totally Self-Checking PLAs," presented at IEEE Built-In-Self-Test Workshop, Charleston, South Carolina, March 27-30, 1985.
P. Bose, D. LaPotin and G. Vijayan, "Performance driven floorplanning for VLSI CPU chips," presented at IEEE Workshop on VLSI, Clearwater, FL, Feb. 1992.
P. Bose and E. S. Davidson, "Techniques in benchmark-driven CPI estimation for VLSI processors," presented at IEEE Workshop on VLSI, Clearwater, FL, Feb. 1992.
P. Bose, S. George, P. Surana, T. Ghosh, N. Roy, S. Pal and D. Dutta Majumder, "CAN-SCAN: an expert system for early detection, self examination guidance and referral service for breast cancer," presented at ASI (Association of Surgeons in India) Annual Conf., Indore, India, December 1990.
P. Bose, "Application-based performance assessment and verification," presented at: ACM Workshop on Pre-Hardware Performance Analysis Techniques held in conjunction with the IEEE/ACM 22nd. Int'l. Symp. on Computer Architecture (ISCA), Italy, June 1995.
P. Bose, "Use of architectural simulation tools in education," presented at: Workshop on Undergraduate Computer Architecture Education, held in conjunction with ISCA-22, Italy, June 1995.
P. Bose and L. Trevillyan, "Compiler support issues for efficient load-store processing," presented at HPCA workshop (Workshop Digest) on: interaction between compilers and computer architectures," San Jose, Feb. 1996.
P. G. Emma and P. Bose, "Computer architecture education in a corporate reengineering program," presented at HPCA workshop on computer architecture education, San Jose, Feb. 1996; also, appeared in IEEE TCCA Newsletter, pp. 17-22, June 1996.
P. Bose and J-D. Wellman, "Compiler-aided loop tuning opportunities in high-end PowerPC(TM) processors," presented at HPCA workshop on interaction between compilers and architectures (Workshop Proceedings), Feb. 1997.

Recent Conference Tutorial Presentations

P. Bose, Tutorial Presentation on: "Architectural simulation methodology for VLSI processors," presented at IEEE International Conference on Computer Architecture, ISCA-21, Chicago, April 1994.
P. Bose and S. Surya, "Pre-silicon performance analysis and validation," tutorial presentation at IEEE/ACM Int'l. Symposium on Computer Architecture (ISCA-23), Philadelphia, May 1996.

Selected Invited Talks at Universities

P. Bose, "Expert Systems for Computer Engineering Problems," presented at Computer Aided Design Seminar Series, Link Hall, Syracuse University, September 18, 1986.
P. Bose, "Heuristics Acquisition and Incorporation in EAVE: an Expert Advisor for Vectorizaton," presented at Center for Supercomputing Research and Development, Talbot Laboratory, University of Illinois, Urbana, December 2, 1986; (updated version presented at Computer Aided Design Seminar Series, Link Hall, Syracuse University, September 18, 1987).
"DEPLOMAT: a Design Expert for PLA Optimization, Maintenance and Test," presented at Center for Integrated Systems, Stanford University, November 19, 1987.
P. Bose, "Interactive Program Improvement Via EAVE: an Expert Adviser for Vectorization," presented at Department of EECS, University of Michigan, Ann Arbor, March 1988.
P. Bose, "Interactive Program Improvement Via EAVE: an Expert Adviser for Vectorization," presented at International Customer Executive (ICX) Seminar on Large-Scale Scientific Computing, La Hulpe, Belgium, March 1988. (Trip paid for by IBM 3090 European Marketing)
P. Bose, "Parallel Test Generation and Fault Simulation", presented at Centre for Development of Advanced Computing (C-DAC), Bangalore, India, June 1990.
P. Bose, "Review of research in VLSI CAD and parallel processing at IBM," presented to Industrial Affiliates Meeting, CUNY, Queens College, NY, January 28, 1991; updated talk on May 30, 1991.
P. Bose, "VLSI CAD and parallel processing: research at IBM and universities," presented at I. I. T., Kharagpur, India, October 4, 1991.
P. Bose, "Early performance estimation and optimization of VLSI super chips," City University of New York, November 13, 1991.
P. Bose, "Fast performance estimation, simulation and enhancement of VLSI CPU logic," presented at Dept. of EE, University of Texas, Austin (sponsored by Computer Engineering Research Center), August 21, 1992.
P. Bose, "Timer-aided performance analysis, timing and verification for advanced super scalar machines," ACAL (EECS) Special Seminar on Parallel Computing, University of Michigan, Ann Arbor, May 26, 1994.

Theses and Selected IBM Technical Reports

P. Bose, "Functional Testing of Programmable Logic Arrays," M.S. Thesis, Electrical Engg., Univ. of Illinois, January 1981.
P. Bose, "Instruction Set Design for Support of High-Level Languages," Ph.D. Thesis, Electrical Engg., Univ. of Illinois, May 1983 (also available as Coordinated Science Laboratory Tech. Rept. R-986, University of Illinois, Urbana, May 1983).
P. Bose, "Functional Testing of Programmable Logic Arrays," IBM Research Report # RC 10681, October 1984.
P. Bose and E. S. Davidson, "Formal Derivation of DEL (DIL) Architectures," IBM Research Report RC 17901, April 1992.
S. Surya, P. Bose and J. A. Abraham, "Architectural timing model validation: PowerPC processor family," IBM Tech. Rept. TR-51.0840, Austin, TX, May 1994.
P. Bose, "Application-based performance analysis and verification," IBM Research Report RC-20102, June 1995.

Selected IBM Technical Disclosure Bulletin (TDB) articles

P. Bose, S. Kim, G. Vijayan, D. LaPotin, "Early floorplanning using critical block transformation for CPI*CT reduction," IBM Technical Bulletin, vol. 36, no. 03, pp. 209-211, March 1993.
P. Bose, "Time attributed dependence graph scheme for prediction of execution time for a block of assignment statements with looping," IBM Technical Disclosure Bulletin, vol. 36, no. 09A, pp. 621-622, Sept. 1993.
P. Bose, "Static architectural loop timer methodology," IBM Technical Disclosure Bulletin, vol. 39, 1996.
P. Bose, M. Charney and P. Emma, "Family of bus protocols to enable timesharing between miss transactions," IBM Technical Disclosure Bulletin, vo. 39, no. 09, September 1996.

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