We will distribute proceedings of the abstracts to the attendees.

Please note that we will not be providing workshop attendees with copies of the presentations. If you are presenting and wish to distribute hardcopy and/or electronic versions of your material, please make your own arrangements to do so.

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Friday, April 30

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Registration:  12:30-13:15

Welcome:  13:15-13:30

Session A:  13:30-15:30
New Architectures and Systems

(20-minute talks, including questions)

• Current Progress in the Design of the Hydra CMP
  Kunle Olukotun, Michael Chen, Lance Hammond, Ben Hubbert, Maciek Kozyrczak, Manohar Prabhu, Michael Siu, and Mark Willey
  Computer Systems Laboratory, Stanford University
• Vortex: Irregular Data Stream Support for Data-Intensive Applications
  Donald Yeung, Nicholas Kohout, Sujata Ramasubramanian, Ilya Khazanov, and Rishi Kurichh
  Systems and Computer Architecture Group, University of Maryland
• Cache Coherence in Page-Based Intelligent Memory
  Diana Keen, Frederic T. Chong, Mark Oskin and Justin Hensley
  Department of Computer Science, University of California at Davis
• Supporting Multiple Coherence Protocols in Programmable Shared Memory Controllers
  Ravindra Kuramkote, John Carter, and Chen-Chi Kuo
  University of Utah
• A Prefetching Technique for Irregular Accesses to Linked Data Structures
  Magnus Karlsson, Fredrik Dahlgren and Per Stenstrom
  Department of Computer Engineering, Chalmers University of Technology
• An Adaptive Cache Coherent Protocol for DSM with Limited Directory Space
  Xiaowei Shen, Arvind and Larry Rudolph
  Laboratory for Computer Science, Massachusetts Institute of Technology

Break:  15:30-16:10

Session B:  16:10-17:50
Databases and Workload Analysis

(20-minute talks, including questions)

• Effectiveness of Off-Chip Caches for Commercial Applications
  Ben Verghese, Luiz Barroso, and Kourosh Gharachorloo
  Compaq Computer Corporation, Western Research Lab
• Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors
  Jim Nilsson and Fredrik Dahlgren
  Dept. of Computer Engineering, Chalmers University of Technology
• A Performance Characterization of TPC-D on HP V-Class Server using Hardware Counters
  Cedric Sims, Ravi Iyer, Laxmi Bhuyan and Ashwini Nanda
  Department of Computer Science, Texas A&M University and IBM TJ Watson Research Center
• On the Instruction-Based Predictability of Producers and Consumers in Shared-Memory Multiprocessors
  Stefanos Kaxiras and Cliff Young
  Bell Labs, Lucent Technologies
• A Case for Non-Strict Cache Coherence: Partially Asynchronous Parallel Genetic Algorithms on a Workstation Cluster
  Siddhartha V. Tambat, Sriram Vajapeyam
  Dept. of Computer Science and Automation, Indian Institute of Science

Session C:  08:00-09:40
Invited Talks on Shared Memory Enterprise Systems

• Cellular Disco: Fault Containment and Resource Management Using Virtual Clusters on Scalable Multiprocessors
  Dan Teodosiu, Kinshuk Govil, Yongqiang Huang, and Mendel Rosenblum
  HP Labs and Stanford University
• Kitchawan and Tornado: Operating System Technology for Shared Memory Multiprocessors
  Orran Krieger
  IBM T.J. Watson Research Center
• System Partitioning for Commercial Platforms
  Tom Lovett
  Sequent Computer Corporation
• Aspects of Main Memory Compression
  Peter Franaszek
  IBM T.J. Watson Research Center

Break:  09:40-10:20

Session D:  10:20-12:00
Tools and Transformations for Cache

(20-minute talks, including questions)

• Code Transformations to Improve Memory Parallelism
  Vijay S. Pai and Sarita Adve
  Department of ECE, Rice University
• An Inexpensive Tool to Understand the Scalability of Applications on Scalable Shared Memory Machines
  Yan Solihin, Vihn Lam and Josep Torrellas
  Univ. of Illinois at Urbana Champaign
• A Study on the Impact of Memory Hierarchy on Stencil Operations for Modern Architectures
  Federico Bassetti, Kei Davis, Olaf Lubeck, Fabrizio Petrini
  Scientific Computing Group, LANL
• Dynamic Task And Data Parallelism Using Space-Time Memory
  Kathleen Knobe, James M. Rehg, Arun Chauhan, Rishiyur S. Nikhil and Umakishore Ramachandran
  Cambridge Research Lab, Compaq Computer Corporation; Rice University; Georgia Tech
• A Multiprocessor Simulation Environment for MIPS Architecture Running on Windows NT/Pentium Platforms
  Henian Zhou and Jih-Kwon Peir
  University of Florida

Lunch:  12:00-13:30

Session E:  13:30-15:10
Software DSMs

(20-minute talks, including questions)

• Scalability of Home-Based Shared Virtual Memory on Clusters of SMPs
  Dongming Jiang, Brian Cokelley, Xiang Yu, Angelos Bilas, and Jashwinder Pal Singh
  Department of Computer Science, Princeton University; Department of Electrical and Computer Engineering, University of Toronto
• File Mapping as a new Parallel File System Interface for a SVM based cluster
  Renaud Lottiaux, Christine Morin
  IRISA
• Fault Tolerant HLRC Distributed Shared Memory
  Florin Sultan, Xiang Yu, Liviu Iftode
  Department of Computer Science, Rutgers University; Department of Computer Science, Princeton University
• High Availability for Software DSM
  Vivekanand Vellanki, Nissim Harel, Namgeun Jeong, Joonwon Lee, Umakishore Ramachandran
  College of Computing, Georgia Tech
• Multithreaded Home-based Lazy Release Consistency Distributed Shared Memory
  Murali Rangarajan and Liviu Iftode
  Department of Computer Science, Rutgers University

Break:  15:10-15:50

Session F:  15:50-17:30
Machines and New Ideas

(20-minute talks, including questions)

• SCASH: Software DSM using High performance network using commodity hardware and software
  Hiroshi Harada, Hiroshi Tezuka, Toshiyuki Takahashi, Shinji Sumimoto, Atsushi Hori, and Yutaka Ishikawa
  Parallel and Distributed System Software Laboratory, RWCP
• The Design Constraints For The Memory Systems Of Useful SMPs
  D.M. Pressel
  Corporate Information and Computing Center, U.S. Army Research Laboratory
• Nautilus: A Third Generation DSM System
  Mario D. Marino and Geraldo L. Campos
  Universidade de Sao Paulo
• A Coherence Protocol for the Elimination of Passive Sharing in Single and Multiple Threaded Shared-Bus Shared-Memory Multiprocessors
  Roberto Giorgi and Cosimo Antonio Prete
  University of Alabama and University of Pisa
• Experiences with Blocking and Non-Blocking Synchronization Mechanisms in SCRAMNet+ Systems
  Steve Menke and Mark Moir
  Westinghouse Corp.; University of Pittsburgh

Workshop conclusion:  17:30

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