Books and Chapters

• D. R. Kaeli, H. Hadimioglu, J. Kuskin, A. K. Nanda and J. Torrellas, "High Performance Memory Systems," Springer-Verlag, 2004.
• A.K. Nanda and L.N. Bhuyan, "Design and Analysis of Cache Coherent Multistage Interconnection Networks," Interconnection Networks for High Performance Parallel Computers, ed. I.D. Scherson and A.S. Youssef, IEEE Computer Society Press, 1994.

Refereed Journals .

• B. D'Amora, A. K. Nanda, K. Magerlein, A. Binstock and B. Yee, "Physics Based On-Line Games on Cell Blades," to appear in IBM Systems Journal, Jan 2006.
• K. Keeton, R. M. Clapp and A.K. Nanda, Guest Editors' Introduction: Evaluating Servers with Commercial Workloads, IEEE Computer, Feb. 2003, pp 29-32.
• M. Dubois, J. Jeong and A. K. Nanda, "Shared Cache Architectures for Decision Support Systems," Performance Evaluation, Vol. 49, Sept. 2002, pp 283-298.
• Y. Hu, Q. Yang and A.K. Nanda, "Measurement, Analysis and Performance Improvement of Apache Web Server," International Journal of Computers and their Applications, Dec. 2001
• A. K. Nanda, A-T. Nguyen,  M. Michael, D. Joseph, “High Throughput Coherence Control and Hardware Messaging in Everest,” IBM Journal of Research and Development, March 2001.
• M. Michael, A.K. Nanda and B.H. Lim, "Coherence Controller Architectures for Scalable Shared Memory Multiprocessors", IEEE Transactions on Computers, pp. 245-255, Feb. '99.
• A.K. Nanda, J. Bondi and S. Dutta, "The Misprediction Recovery Cache," International Journal of Parallel Programming, April 1998.
• U. Ko, P. Balsara and A.K. Nanda, "Power and Performance Optimization for On-Chip Multi Level Cache Hierarchies in Microprocessors", IEEE Transactions on VLSI Systems, pp. 299-308, June 1998.
• L.N. Bhuyan, R. Iyer, T. Askar, A.K. Nanda and M. Kumar, "Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor," IEEE Transactions on Parallel and Distributed Systems, Jan. 1997.
• A.K. Nanda and L.N. Bhuyan, "Efficient Mapping of Applications onto Cache Coherent Multiprocessors," Journal of Parallel and Distributed Computing, Nov. 1993.
• A.K. Nanda and L.N. Bhuyan, "Design and Analysis of Cache Coherent Multistage Interconnection Networks," IEEE Transactions on Computers, April 1993.

Refereed Conferences

• A. K. Nanda, K. K. Mak, K. Sugavanam, R. Sahoo, V. Soundararajan, T. B. Smith, "MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design," ASPLOS 2000, pp 37-48.
• A.K. Nanda, A-T. Nguyen, M. Michael and D. Joseph "High Throughput Coherence Controllers", Proceedings of the 6th International Symposium on High Performance Computer Architecture, HPCA-6, Jan. 2000.
• R. Iyer, L.N. Bhuyan and A.K. Nanda, "Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors", Proceedings of the 12th International Parallel and Distributed Processing Symposium (IPDPS2000), Cancun, Mexico, May 2000.
• M. Michael and A.K. Nanda, "Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors", Proceedings of the 5th International Symposium on High Performance Computer Architecture, HPCA-5, Jan. 1999.
• Y. Hu, Q. Yang and A.K. Nanda, "Measurement, Analysis and Performance Improvement of Apache Web Server," Proceedings of the 18th IPCCC, Feb. 1999.
• A.K. Nanda, Y. Hu, M. Ohara, M. Giampapa, C. Benveniste and M. Michael, "The Design of COMPASS : An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors," Proceedings of International Parallel Processing Symposium, April 1998.
• M. Michael, A.K. Nanda, B-H. Lim and M. Scott, "Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors," Proceedings of the 24th International Symposium on Computer Architecture, June 1997.
• A-T. Nguyen, M. Michael, A.K. Nanda, K. Ekanadham and P. Bose `Accuracy and Speed-Up of Parallel Trace-driven Architectural Simulation," Proceedings of International Parallel Processing Symposium, April 1997. .
• A.K. Nanda, J. Bondi and S. Dutta, "Integrating a Misprediction Recovery Cache(MRC) into a Superscalar Processor," Proc. of International Symposium on Microarchitecture, Micro'29, Dec. 1996.
• L.N. Bhuyan, A.K. Nanda and T. Askar, "Performance and Reliability of the Multistage Bus Network," Proceedings of the International Conference on Parallel Processing, August 1994.
• A.K. Nanda and L.N. Bhuyan, "Mapping Applications onto a Cache Coherent Multiprocessor," Supercomputing'92, Nov. 1992.
• A.K. Nanda and L.N. Bhuyan, "A Formal Specification and Verification Technique for Cache Coherence Protocols," Proceedings of the International Conference on Parallel Processing, August 1992.
• A.K. Nanda, D. DeGroot and D. Stenger, "Scheduling Directed Task Graphs on Multiprocessors using Simulated Annealing Algorithms," Proceedings of the 12th International Conference on Distributed Computing Systems, June 1992.
• A.K. Nanda and Hong Jiang, "Analysis of Directory Based Cache Coherence Schemes with Multistage Networks," ACM Computer Science Conference, march 1992.
• L.N. Bhuyan and A.K. Nanda, "Multistage Bus Network(MBN) : An Interconnection Network for Cache Coherent Multiprocessors," Proceedings of the 3rd International Symposium on Parallel and Distributed Processing, Dec. 1991.