This paper describes, in a manner that is meant to be amenable to both mathematicians and engineers, the accurate optimization of transistor sizes on a static timing basis. Delays of individual gates (and gradients thereof) are obtained by transient (i.e. time-domain) simulation rather than simplified Elmore or analytical Slews (rise/fall times)[§] and their effects on delay are correctly taken into account. The optimization problem is stated in a form amenable to general-purpose nonlinear optimization. However, the size and inherent degeneracy of the resulting optimization problem make it difficult to solve. By considering the structure of the problem, optimality conditions are derived and conditions can be exploited to carry out the tuning more effectively and efficiently. Numerical results from the optimization of high-performance microprocessor circuits are presented. Further, an investigation of the viability and merits of an implementation of Lagrangian Relaxation in the same circuit optimization environment are detailed.
[§]The slew of a signal is the rate at which it changes. Some simplified models ignore the impact of input slew on the delay of a logic gate.
Circuit optimization, Lagrangian relaxation, optimality conditions.