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    Chip Checker
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Chip Checker

EinsTuner automates the transistor-design process.

By Stewart Wolpin

You turn an orange row and your solid red side is no longer solid. So you twist the blue row and now the white side looks like a checkerboard. Flip a row of green, red and white squares to fill your green side, but now your perfect orange side resembles a painting by Mondrian.

Anyone who's wrestled with a Rubik's Cube® has an inkling of what chip designers go through when trying to optimize transistor designs. The quest to achieve a particular cycle time of total picoseconds (a trillionth of a second) is somewhat similar to solving the once-popular puzzle. Just like when you turn the rows of a Rubik's Cube, tweaking the parameters of one transistor alters the performance of recently optimized adjacent transistors. And making transistors larger speeds them up, but it could slow down neighboring transistors. Designers can only achieve state-of-the-art clock speeds if they can squeeze every last picosecond out of the millions of possible paths through the millions of transistors on a chip.

Solving a 54-squared Rubik's Cube, with its comparatively miniscule 43 quintillion possible combinations, is child's play. After all, a person attempting to master the Rubik's Cube faces a finite number of choices. By contrast, tuning a circuit is a continuous problem involving an infinite number of choices. So sitting in front of a workstation and optimizing a multi-million-transistor chip, transistor-by-transistor, is the microprocessor equivalent of working on a series of Rubik's Cubes, each with a million sides and each with an infinite number of possible solutions.

"Manual tuning is a drudgery," says Greg Northrop, an IBM Research staff member based at the Thomas J. Watson Research Center in Yorktown Heights, N.Y. "It's something you have to go through with a fine tooth comb. You have to understand what you can tune and what things you have to change to get to the cycle time you want."

If the designer is lucky, optimizing just one set of transistors can take weeks. Usually it takes months. And all this tweaking and tuning has to happen on schedule and before the design is committed to silicon.

The breakthrough
For years, IBM has investigated various methods to automate the transistor optimizing process. In January 2001, IBM finalized a revolutionary transistor-optimizing CAD (computer-aided design) software solution code-named EinsTuner.

In addition to its pun on Einstein, the name comes from the German word "eins" meaning "one." This alludes to the fact that the software is a single, integrated tuning tool. Using the power of mathematical nonlinear optimization algorithms—an advanced mathematical recipe to minimize the number of potential solutions—EinsTuner guarantees the optimal tuning of circuits containing up to 50,000 transistors. The software guarantees this optimization not in weeks or months, but typically in fewer than six hours.

EinsTuner gives chips an overall performance jump of 15 to 20 percent. But unlike IBM's other recent chip innovations—the 1997 transition from aluminum to copper wiring, which brought about a 10 percent performance improvement, and the adoption of silicon-on-insulator technology in 1999, which added a 12 to 15 percent enhancement—EinsTuner doesn't require a multi-million dollar investment in materials, tooling or manufacturing.

"EinsTuner is an extremely modest development effort in comparison," says Watson-based Chandu Visweswariah, EinsTuner's primary developer. "You hire a few skilled people and give them keyboards and you have a software tool for improving chip performance."

These advantages—faster chips designed in less time at a low cost—give IBM an enormous competitive advantage in the chip marketplace. IBM's present generation of popular IBM zSeriesTM mainframe servers, for instance, feature EinsTuner-tuned microprocessors. And in March 2002, market research company International Data Corporation reported that IBM surged from third to first in UNIXTM server sales in the fourth quarter of 2001. This surge comes courtesy of the p690 eServer, powered by the industry's first 64-bit chip, which contains a staggering 159 million transistors.

Components in concert
So how does EinsTuner perform its speedy feats of automated legerdemain? Because the problem is more complicated than simply automating a repetitive manual operation, EinsTuner combines several components that perform individual tasks in sequence.

The software breaks down a circuit into sub-circuits, each timed by a program code-named SPECS (Simulation Program for Electronic Circuits and Systems) to predict the circuit's timing, or delay. A static transistor-level timer code-named EinsTLT traces the paths to determine whether the circuit meets its pre-determined design time parameters, or delay budget.

Another EinsTuner component code-named LANCELOT (Large and Nonlinear Constrained Extended Lagrangian Optimization Techniques) runs new static timer simulations on the newly sized transistors, repeatedly tweaking them until the optimum size/speed solution is reached.

One of EinsTuner's more remarkable features is its multi-dimensional global view of all the interacting paths. EinsTuner uses patented advanced algorithms to reduce or "prune" the number of optimization variables, and reduce or "constrain" the number of theoretically infinite transistor sizes, thereby making the resulting nonlinear optimization problem easier to solve.

"Suppose I'm sailing in a lake and you ask me to find its deepest point," explains Visweswariah. "I would put an anchor down and take a depth measurement. Then I'd sail in all four directions some distance and take more depth measurements and finally discover the direction of the slope, which eventually leads you to the deepest point.

"But what if I told you that if you dropped the anchor just once, I could tell you not only the depth but in what direction the floor was sloping at that point? That would make the job of finding the deepest point so much easier. It turns out that if you want to use software to solve nonlinear optimization problems in anything more than 20 or 30 dimensions, you can't do it without these gradients and sensitivities. For the first time ever, we have a practical method for computing them efficiently instead of 'dropping the anchor' so many times."

To make this work, all a designer has to do is enter or adjust a half dozen default transistor constraint parameters (i.e. a pre-determined cycle time budget and project-specific transistor size restrictions) into a deceptively simple four-screen graphical user interface (GUI), then press a button. Four to six hours later, EinsTuner is done and the designer is free to work on the next circuit design.

Unintended benefits
Imagine that each Rubik's Cube you painstakingly finish is simply one pixel in a wall-sized picture. It would be awfully hard to concentrate on the finished picture given the number of Cubes you need to complete. Cutting transistor optimizing time from months to hours means designers spend a lot less time staring at transistor schematics on their workstation screens. This allows them to concentrate not on the minutia of transistor tweaking but on that big picture—the overall design of the circuit.

"You can simply sketch the unsized schematic knowing that EinsTuner will optimize it," explains Ee Cho, an IBM design tool and methodology engineer based in Poughkeepsie, N.Y., who designed the EinsTuner GUI. "The real impact isn't that it made the circuit faster, but it helped people design more productively."

EinsTuner also represents some theoretical breakthroughs that could only have been accomplished in a multidisciplinary, R&D-oriented environment. "This project could stand on its own merits on the basis of research alone," asserts Andy Conn, the Yorktown Heights-based mathematician who developed EinsTuner's nonlinear optimization algorithms. "We're making contributions to the academic side of optimization research that are worth just as much as the applied side."

An EinsTuner future
Perhaps most important, EinsTuner helps close the so-called productivity gap, the difference between the theoretical number of transistors that can be squeezed onto a chip, and the number of transistors that a human being can realistically imagine, design and use in a circuit.

"It will soon be possible to place a billion logic transistors on a chip, but who's going to design a circuit that has a billion transistors and makes good use of all of them?" poses Visweswariah. "EinsTuner helps bridge this gap and reduces the time it takes to create large, complicated, custom-designed circuits."

This capability will help IBM leapfrog past its competitors with chips that are larger, faster and more complex. For instance, researchers are now applying EinsTuner to the new microprocessor for the company's next-generation zSeries mainframe server, as well as to a project code-named "Cell," a cutting-edge game processor that IBM is developing with Sony and Toshiba.

"EinsTuner is a unique tool that no one else in the industry has," says Dale Hoffman, director of IBM's Fishkill-based Electronic Design Automation laboratory. "In terms of custom designer productivity, it's probably the top tool that has ever been developed."

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