This research project investigates power and complexity-aware microprocessor design, analysis, and validation. The two main goals of this project are (1) to innovate and evaluate novel microarchitectures and (2) to develop a robust modeling and validation infrastructure to support this research. In order to achieve the first goal, designs must be complexity-aware. Two major modern constraints are power consumption and verification cost, which are two indices of complexity. In addition, verification cost determines time-to-market. As part of the first goal, we are learning how to build tomorrow's processors which will allow scalable system performance with manageable growth in power and verification complexity. In order to achieve the second goal, we first need power-performance modeling. Next, we need to integrate energy models into traditional timers. Circuit-level tools will be used to obtain power statistics to build the energy models.

University Ties

• Prof. David H. Albonesi at the University of Rochester, Prof. Margaret Martonosi at Princeton University.

Other Related University Collaborators

• Prof. James E. Smith at the University of Wisconsin, Prof. Edward S. Davidson at the University of Michigan.

Recent Invited Tutorial

• "Power-performance modeling and validation," M. Martonosi, D. Brooks, P. Bose, 7th International Symposium on High Performance Computer Architecture (HPCA), Jan. 2001.

Recent Conference Presentations

• "Power-performance modeling and tradeoff analysis for a high-end microprocessor," D. Brooks, M. Martonosi, P. Bose, Proc. Power-Aware Computer Systems Workshop (PACS), held in conjunction with ASPLOS conference, Nov. 12, 2000. Available as IBM Research Report RC21875, Nov. 2000.

• "An adaptive issue queue for reduced power at high performance," A. Buyuktosunoglu, S. Schuster, P. Cook, P. Bose, D. Brooks, D. Albonesi, Proc. Power-Aware Computer Systems Workshop (PACS), held in conjunction with ASPLOS conference, Nov. 12, 2000. Available as IBM Research Report RC21874, Nov. 2000.

• "Simulation in the small: the case for simpler models and test cases in computer architecture education and research," P. Bose, Proc. ISCA Workshop on Computer Architecture Education, June, 2000. Available as IBM Research Report RC21821, 2000.

• "Performance and functional verification of microprocessors," P. Bose and J. A. Abraham, Proc. IEEE VLSI Design Conference, Jan. 2000, pp. 58-63.

Recent Journal Publications

• "Power-aware microarchitecture: design and modeling challenges for the next generation microprocessors," D. Brooks, P. Bose, S. Schuster, H. Jacobson, P. Kudva, A. Buyuktosunoglu, J-D. Wellman, V. Zyuban, M. Gupta, P. Cook, IEEE Micro, vol. 20, no. 6 Nov/Dec 2000, pp. 26-44, IBM Research Report RC21876, Nov, 2000.

• "Testing for function and performance: towards an integrated processor validation methodology," P. Bose, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 16, nos. 1/2, Feb/Apr 2000, pp. 58-63.

Related Work

• The MET: Microarchitecture Exploration Toolset.

Contact

• Pradip Bose (pbose@us.ibm.com)