The purpose of the Ultra high frequency microarchitecture project is
to study the challenges and opportunities afforded by the future use
of ultra high frequency designs. This effort continues an IBM focus on
high frequency designs, including guTS, BOA (a second generation DAISY
system), and the power/performance study of deeply pipelined
microarchitectures. The team brings together many of the researchers
who previously were instrumental in defining the BOA and CELL
architectures.
Challenges of ultra high frequency microarchitectures studied are
latency-aware design of memory hierarchies for both instruction and
data delivery, low-complexity high frequency pipeline design, and
power analysis. Another aspect of this project is to understand the
future circuit technology constrains and design styles, and their
impact on microarchitecture.
-
Pipeline control for high-frequency pipelined designs
-
M.K. Gschwind
02/20/2000 Issued as US patent 6192466 Top 10% Licensing Award
- Integrated Analysis of Power and Performance for Pipelined
Microprocessors
- IBM Research Report RC22913, IBM T.J. Watson Research Center,
Yorktown Heights, NY, April 2003. (Pradip Bose, David M. Brooks,
Philip G. Emma, Michael K. Gschwind, Vijayalakshmi Srinivasan, Philip
N. Strenski, Victor Zyuban).
- Optimizing Pipelines for Power and Performance
- ACM/IEEE 35th International Symposium on Microarchitecture, Istanbul,
Turkey, November 2002. (V. Srinivasan, D. Brooks, M. Gschwind,
P. Bose, P. Emma, V. Zyuban, P. Strenski) Best IBM Research
Paper 2002
- Inherently Lower
Complexity Architectures using Dynamic Optimization
- Proc. Workshop on Complexity Effective Design in conjunction with
ISCA-2002, Anchorage, AK, May 2002. (M. Gschwind, E.R. Altman)
-
High Frequency Pipeline Architecture Using the Recirculation
Buffer [fulltext]
- Michael Gschwind, Stephen Kosonocky, Erik Altman
IBM Research Report RC 23113, March 2001
- Dynamic
and Transparent Binary Translation
- IEEE Computer, March 2000.
(M. Gschwind, E. Altman, S. Sathaye, P. Ledak, D. Appenzeller) IEEE Computer Cover Story
- BOA: The Architecture of a Binary Translation Processor
- IBM Research Report RC21665, IBM T.J. Watson Research Center,
Yorktown Heights, NY, December 1999.
(E. Altman, M. Gschwind, S. Sathaye, S. Kosonocky, A. Bright,
J. Fritts, P. Ledak, D. Appenzeller, C. Agricola, Z. Filan)
- BOA: Targeting Multi-Gigahertz with Binary Translation
- 1999 Workshop on Binary Translation in conjunction with PACT '99, Newport Beach, CA, October 1999.
IEEE Computer Society Technical Committe on Computer Architecture
Newsletter, December 1999.
( S. Sathaye, P. Ledak, J. LeBlanc, S. Kosonocky, M. Gschwind,
J. Fritts, Z. Filan, A. Bright, D. Appenzeller, E. Altman,
C. Agricola) Best Paper Award
- A 1.0-GHz single-issue 64-bit powerPC integer processor
- Journal of Solid State Circuits, Vol. 33, No. 11, Nov 1998.
(J. Silberman et al.)
IEEE
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