CMOS link circuits


The continued shrinking of CMOS feature sizes allows us to build high-speed interconnect circuits at ever higher data rates.

We explore new circuit architectures for transmitter and receiver circuits together with next-generation CMOS technology. The goal is to achieve the highest possible data rate at the lowest power consumption and smallest chip area.

Typical circuits include


Figure 1. A 20 Gb/s, four-level pulse amplitude modulated (PAM-4) signal [2004-4].


Figure 2. Chip layout of high-bandwidth amplifier circuit using integrated inductors [2005-2].