Read/write schemes, signal processing and coding, modeling/simulation

In order for phase change memory to become a viable technology for high-volume manufacturing, its reliability has to be brought to levels similar to those of incumbent technologies.

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Histogram of the programmed resistance levels in a cell array

Figure 1. Histogram of the programmed resistance levels in a cell array upon application of an iterative programming scheme. Owing to the adaptive nature of such a scheme, confinement of programmed levels is achieved. In this example, it is possible to pack 16 levels into the available resistance range.

Multilevel cell (MLC) phase change memory (PCM) is subject to several reliability concerns, the identification and effective mitigation of which are at the center of our activities.

Process and material variability cause variations in the effective memory cell size across arrays of cells. To program multiple resistance levels accurately, it is necessary to employ iterative programming strategies, as opposed to single voltage/current pulses, which give rise to broad signal distributions.

Iterative programming, however, comes with higher latency and energy costs, which need to be contained. We conduct research on the definition of novel iterative programming schemes that combine low latency (fast convergence in a few iterations), low energy dissipation per bit, and robustness to cell variability (tight confinement of the programmed resistance distributions across arrays of cells) (Fig. 1) [2011-1].

Resistance drift adversely affects the reliability of MLC storage in PCM because the distance between adjacent levels is small, and stochastic fluctuations of the resistance are more likely to cause level overlap over time (Fig. 2).

Drift phenomenon

Figure 2. Illustration of the drift phenomenon: Histogram of the cell contents from an array of PCM cells programmed at four resistance levels and monitored at different times after programming. Drift causes a shift of the programmed levels over time. The x-axis, labeled ADC Code, is inversely proportional to cell resistance.


We devise new metrics of the state of an MLC PCM cell that are more accurate estimates of the programmed quantity, i.e., the amorphous phase thickness, than the conventional electrical resistance. These metrics are significantly more resilient to drift than the low-field resistance and offer increased level contrast and noise immunity (Fig. 3). Experiments and simulations attest to the superior reliability of the drift-resilient metrics for MLC PCM [2011-4, 2011-8].

In MLC memories, where the level distributions change as a function of time (such as in PCM due to drift), cell wear (such as in Flash memory), or due to other phenomena, the use of fixed thresholds to detect the stored data can lead to a very rapid accumulation of errors. In such cases, either the thresholds need to be adapted—at the cost of higher complexity—or the data must be refreshed—at the cost of higher latency and more cell wear.

We are developing signal processing methods to adapt the detection thresholds in order to minimize the probability of level error at all times and throughout the device lifetime (Fig. 4). At the same time, we are introducing modulation coding schemes, in which the user data are encoded in short codewords. In these schemes, information is stored in the relative order of levels/symbols in a codeword. This feature provides additional immunity to drift, on top of that offered by the use of adaptive thresholds [2011-2, 2013-1].

We are performing extensive characterization studies on PCM cells and cell arrays to understand basic electrical properties and to extract statistical reliability information, respectively [2013-4]. Based on the experimental data, the parameters of empirical models that capture the drift and noise characteristics are extracted. Statistical channel simulators are then used to estimate the memory array performance given a maximum error rate budget and a retention time target [2012-1].

Comparison of drift resilience of new cell-state metric with conventional low-field resistance metric

Figure 3. Comparison of conventional low-field resistance metric (left) with drift resilience of new cell-state metric (right). In both cases, the metric evolution in time follows a power law, with each programmed cell level corresponding to a different exponent. The proposed drift-resilient metric exhibits significantly less drift, and thus offers improved reliability.


Comparison of the fixed threshold vs adaptive threshold strategy for the detection of stored levels in MLC PCM.

Figure 4. Comparison of the fixed threshold (left) vs adaptive threshold (right) strategy for the detection of stored levels in multilevel cell phase change memory. The level means and variances change over time due to drift (shaded areas represent 3-sigma variation around the mean values, shown in solid lines). Employing adaptive thresholds leads to largely enhanced retention.