Moriyoshi Ohara  IBM Research Division, Tokyo Research Laboratory, 1623-14, Shimotsuruma, Yamatoshi, Kanagawa-ken, 242-8502, Japan (ohara@jp.ibm.com). Dr. Ohara received a B.S. degree in mathematical engineering from the University of Tokyo in 1986, and M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1992 and 1996, respectively. He joined the IBM Tokyo Research Laboratory in 1986 and has worked on multiprocessor systems, ultra high-resolution display systems, and performance simulation tools. Dr. Ohara's current research interests include high-performance parallel architectures and microprocessor architectures.

Hiroshi Inoue  IBM Research Division, Tokyo Research Laboratory, 1623-14, Shimotsuruma, Yamatoshi, Kanagawa-ken, 242-8502, Japan (inouehrs@jp.ibm.com). Mr. Inoue received B.S. and M.S. degrees in system design engineering from Keio University in 2000 and 2002, respectively. He joined the IBM Tokyo Research Laboratory in 2002 and has worked in the area of optimization techniques for the Cell Broadband Engine™ architecture and the PowerPC^® architecture. His research interests include high-performance architectures and optimization techniques for high-performance computing workloads.

Yukihiko Sohda  IBM Research Division, Tokyo Research Laboratory, 1623-14, Shimotsuruma, Yamatoshi, Kanagawa-ken, 242-8502, Japan (sohda@jp.ibm.com). Dr. Sohda received B.S., M.S., and Ph.D. degrees from the Tokyo Institute of Technology in 1998, 2000, and 2003, respectively. He joined the IBM Tokyo Research Laboratory, where he has worked on Web-service caching. His research interests include high-performance parallel architectures.

Hideaki Komatsu  IBM Research Division, Tokyo Research Laboratory, 1623-14, Shimotsuruma, Yamatoshi, Kanagawa-ken, 242-8502, Japan (komatsu@jp.ibm.com). Dr. Komatsu received B.S. and M.S. degrees in electrical engineering from Waseda University in 1983 and 1985, respectively, and a Ph.D. degree in computer science in 1998. He joined the IBM Tokyo Research Laboratory in 1983, where he has carried out research activity in many areas. His research interests include compiler optimization techniques and high-performance architectures.

Toshio Nakatani  IBM Research Division, Tokyo Research Laboratory, 1623-14, Shimotsuruma, Yamatoshi, Kanagawa-ken 242-8502, Japan (nakatani@jp.ibm.com). Dr. Nakatani received a B.S. degree in mathematics from Waseda University in 1975 and M.S.E. and M.A., degrees from Princeton University in 1985. He received a Ph.D. degree in computer science from Princeton University in 1987, when he also joined the IBM Tokyo Research Laboratory. Dr. Nakatani is currently an IBM Distinguished Engineer and manager of the Systems Group. His research interests include computer architectures, optimizing compilers, and algorithms for parallel computer systems.