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Historically, the steady growth of computer system performance depended on the performance of microprocessors, which depended on the scaling of devices and circuits to smaller dimensions. As scaling on the 2D surface of chips approaches practical limits, 3D technologies offer an opportunity for continued system improvements, even as the progress of scaling slows down. The eight papers in this issue describe the system design opportunities and challenges of 3D chip technology, as well as methods for producing dense arrays of through-silicon vias, thinned silicon, dense area-array silicon–silicon interconnection, chip stacking, and 3D wafer integration. Thermomechanical modeling and the implementation of 3D structures in products are also described.
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3D Chip Technology
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Preface
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J. U. Knickerbocker, Guest Editor
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p. 539
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Is 3D chip technology the next growth engine for performance improvement?
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P. G. Emma and E. Kursun
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p. 541
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Three-dimensional silicon integration
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J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright
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p. 553
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Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
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P. S. Andry, C. K. Tsang, B. C. Webb, E. J. Sprogis, S. L. Wright, B. Dang, and D. G. Manzer
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p. 571
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Wafer-level 3D integration technology
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S. J. Koester, A. M. Young, R. R. Yu, S. Purushothaman, K.-N. Chen, D. C. La Tulipe Jr., N. Rana, L. Shi, M. R. Wordeman, and E. J. Sprogis
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p. 583
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3D chip stacking with C4 technology
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B. Dang, S. L. Wright, P. S. Andry, E. J. Sprogis, C. K. Tsang, M. J. Interrante, B. C. Webb, R. J. Polastre, R. R. Horton, C. S. Patel, A. Sharma, J. Zheng, K. Sakuma, and J. U. Knickerbocker
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p. 599
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3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
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K. Sakuma, P. S. Andry, C. K. Tsang, S. L. Wright, B. Dang, C. S. Patel, B. C. Webb, J. Maria, E. J. Sprogis, S. K. Kang, R. J. Polastre, R. R. Horton, and J. U. Knickerbocker
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p. 611
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Thermomechanical modeling of 3D electronic packages
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S. M. Sri-Jayantha, G. McVicker, K. Bernstein, and J. U. Knickerbocker
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p. 623
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Through-silicon vias enable next-generation SiGe power amplifiers for wireless communications
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A. J. Joseph, J. D. Gillis, M. Doherty, P. J. Lindgren, R. A. Previti-Kelly, R. M. Malladi, P.-C. Wang, M. Erturk, H. Ding, E. G. Gebreselasie, M. J. McPartlin, and J. Dunn
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p. 635
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Author index for Volume 52
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p. 649
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Subject index for Volume 52
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p. 657
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Erratum
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p. 663
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