|
|
|
|
|
|
Radiation can cause transistors to change their state and induce soft errors in computers. As transistor density and performance of CMOS (complementary metal-oxide semiconductor) devices increase, the reduced transistor size and low-power operation of the devices require that greater emphasis be placed on the understanding and control of soft errors in devices, circuits, and final system applications. The nine papers in this issue highlight the current understanding of the soft error rate (SER) in CMOS devices, circuits, and servers. The role of alpha-particles (helium nuclei), mitigation strategies, physics-based nuclear models, device design, treatment of experimental data, and strategies for reducing SERs in complex servers are described and reviewed.
|
|
|
|
|
|
|
|
Soft Errors in Circuits and Systems
|
|
|
|
|
|
|
|
Message from the Vice President, Science and Technology, IBM Research Division
|
|
T.-C. Chen
|
|
|
|
|
|
|
|
|
Preface
|
|
D. F. Heidel, J. Hergenrother, and K. P. Rodbell, Guest Editors
|
p. 223
|
|
|
|
|
|
|
|
Alpha-particle-induced upsets in advanced CMOS circuits and technology
|
|
D. F. Heidel, K. P. Rodbell, E. H. Cannon, C. Cabral, Jr., M. S. Gordon, P. Oldiges, and H. H. K. Tang
|
p. 225
|
|
|
|
|
|
|
|
SEMM-2: A new generation of single-event-effect modeling tools
|
|
H. H. K. Tang
|
p. 233
|
|
|
|
|
|
|
|
New simulation methodology for effects of radiation in semiconductor chip structures
|
|
H. H. K. Tang, C. E. Murray, G. Fiorenza, K. P. Rodbell, M. S. Gordon, and D. F. Heidel
|
p. 245
|
|
|
|
|
|
|
|
Circuit design and modeling for soft errors
|
|
A. KleinOsowski, E. H. Cannon, P. Oldiges, and L. Wissel
|
p. 255
|
|
|
|
|
|
|
|
Single-event-upset and alpha-particle emission rate measurement techniques
|
|
M. S. Gordon, K. P. Rodbell, D. F. Heidel, C. Cabral, Jr., E. H. Cannon, and D. D. Reinhardt
|
p. 265
|
|
|
|
|
|
|
|
Soft-error resilience of the IBM POWER6 processor
|
|
P. N. Sanda, J. W. Kellington, P. Kudva, R. Kalla, R. B. McBeth, J. Ackaret, R. Lockwood, J. Schumann, and C. R. Jones
|
p. 275
|
|
|
|
|
|
|
|
Soft-error resilience of the IBM POWER6 processor input/output subsystem
|
|
C. Bender, P. N. Sanda, P. Kudva, R. Mata, V. Pokala, R. Haraden, and M. Schallhorn
|
p. 285
|
|
|
|
|
|
|
|
Phaser: Phased methodology for modeling the system-level effects of soft errors
|
|
J. A. Rivers, P. Bose, P. Kudva, J.-D. Wellman, P. N. Sanda, E. H. Cannon, and L. C. Alves
|
p. 293
|
|
|
|
|
|
|
|
System RAS implications of DRAM soft errors
|
|
T. J. Dell
|
p. 307
|
|
