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IBM Journal of Research and Development

Advanced Silicon Technology Volume 50, Number 4/5, 2006 Click to enlarge
RD 50-4/5
Device scaling has dominated the advancement of silicon device technology for the last three decades ensuring a performance gain of approximately 35% per technology generation. We are now entering an era in which simple device scaling is limited by chip power and manufacturing constraints. The papers in this issue describe solutions in device design and material research required to continue the performance trend. The implementation of silicon technology with low voltage operation or three-dimensional integration is also discussed.
Table of Contents Papers in: HTML   PDF Order No. G322-0248-00
Advanced Silicon Technology
Message from the Vice President, Science and Technology, IBM Research Division T.-C. Chen
Preface W. Haensch and M. Ieong, Guest Editors p. 337
Silicon CMOS devices beyond scaling W. Haensch, E. J. Nowak, R. H. Dennard, P. M. Solomon, A. Bryant, O. H. Dokumaci, A. Kumar, X. Wang, J. B. Johnson, and M. V. Fischetti p. 339
Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations D. A. Antoniadis, I. Aberg, C. Ní Chléirigh, O. M. Nayfeh, A. Khakifirooz, and J. L. Hoyt p. 363
Germanium channel MOSFETs: Opportunities and challenges H. Shang, M. M. Frank, E. P. Gusev, J. O. Chu, S. W. Bedell, K. W. Guarini, and M. Ieong p. 377
Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges E. P. Gusev, V. Narayanan, and M. M. Frank p. 387
Emerging nanoscale silicon devices taking advantage of nanostructure physics T. Hiramoto, M. Saitoh, and G. Tsutsui p. 411
Optimizing CMOS technology for maximum performance D. J. Frank, W. Haensch, G. Shahidi, and O. H. Dokumaci p. 419
High-performance CMOS variability in the 65-nm regime and beyond K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer p. 433
Product-representative “at speed” test structures for CMOS characterization M. B. Ketchen and M. Bhushan p. 451
Ultralow-voltage, minimum-energy CMOS S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak, and D. M. Sylvester p. 469
Three-dimensional integrated circuits A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong p. 491
Regular paper
Victim management in a cache hierarchy P. A. Franaszek, L. A. Lastras-Montaño, S. R. Kunkel, and A. C. Sawdey p. 507

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