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IBM Journal of Research and Development

Exploratory Systems Research Volume 50, Number 2/3, 2006 Click to enlarge
RD 50-2/3
Exploratory systems research focuses on technologies that will make future systems faster, lower-power, more reliable, more expandable, easier to use, and easier to design. Systems range from small embedded devices to installations with thousands of processors with petabytes of storage. This issue contains 13 papers on large systems built from relatively simple parts, systems management and use, and the design of circuits, architectures, and tools for future processors.
Table of Contents Papers in:     Order No. G322-0247-00
Exploratory Systems Research
Preface E. Altman and S. Sathaye, Guest Editors p. 169
Composing large systems from simple components
Systems research challenges: A scale-out perspective T. Agerwala and M. Gupta p. 173
IBM Intelligent Bricks project—Petabytes and beyond W. W. Wilcke, R. B. Garner, C. Fleiner, R. F. Freitas, R. A. Golding, J. S. Glider, D. R. Kenchammana-Hosekote, J. L. Hafner, K. M. Mohiuddin, KK Rao, R. A. Becker-Szendy, T. M. Wong, O. A. Zaki, M. Hernandez, K. R. Fernandez, H. Huels, H. Lenk, K. Smolin, M. Ries, C. Goettert, T. Picunko, B. J. Rubin, H. Kahn, and T. Loo p. 181
Reliability of modular mesh-connected intelligent storage brick systems C. Fleiner, R. B. Garner, J. L. Hafner, KK Rao, D. R. Kenchammana-Hosekote, W. W. Wilcke, and J. S. Glider p. 199
Using and managing large systems
Braids and fibers: Language constructs with architectural support for adaptive responses to memory latencies D. F. Bacon and X. Shen p. 209
Self-adapting numerical software (SANS) effort J. Dongarra, G. Bosilca, Z. Chen, V. Eijkhout, G. E. Fagg, E. Fuentes, J. Langou, P. Luszczek, J. Pjesivac-Grbovic, K. Seymour, H. You, and S. S. Vadhiyar p. 223
Performance and environment monitoring for continuous program optimization C. Caşcaval, E. Duesterwald, P. F. Sweeney, and R. W. Wisniewski p. 239
Building web services for scientific grid applications G. Kandaswamy, L. Fang, Y. Huang, S. Shirasuna, S. Marru, and D. Gannon p. 249
HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection R. Shetty, M. Kharbutli, Y. Solihin, and M. Prvulovic p. 261
Processors, circuits, architecture, tools
Limited switch dynamic logic circuits for high-speed low-power circuit design W. Belluomini, D. Jamsek, A. K. Martin, C. McDowell, R. K. Montoye, H. C. Ngo, and J. Sawada p. 277
Decomposing the load–store queue by function for power reduction and scalability L. Baugh and C. Zilles p. 287
High-quality ISA synthesis for low-power cache designs in embedded microprocessors A. C. Cheng and G. S. Tyson p. 299
Modeling wire delay, area, power, and performance in a simulation infrastructure N. P. Carter and A. Hussain p. 311
Application of full-system simulation in exploratory system design and development J. L. Peterson, P. J. Bohrer, L. Chen, E. N. Elnozahy, A. Gheith, R. H. Jewell, M. D. Kistler, T. R. Maeurer, S. A. Malone, D. B. Murrell, N. Needel, K. Rajamani, M. A. Rinaldi, R. O. Simpson, K. Sudeep, and L. Zhang p. 321
Erratum   p. 333

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