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Exploratory systems research focuses on technologies that will make future systems faster, lower-power, more reliable, more expandable, easier to use, and easier to design. Systems range from small embedded devices to installations with thousands of processors with petabytes of storage. This issue contains 13 papers on large systems built from relatively simple parts, systems management and use, and the design of circuits, architectures, and tools for future processors.
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Exploratory Systems Research
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Preface
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E. Altman and S. Sathaye, Guest Editors
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p. 169
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Composing large systems from simple components
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Systems research challenges: A scale-out perspective
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T. Agerwala and M. Gupta
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p. 173
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IBM Intelligent Bricks project—Petabytes and beyond
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W. W. Wilcke, R. B. Garner, C. Fleiner, R. F. Freitas, R. A. Golding, J. S. Glider, D. R. Kenchammana-Hosekote, J. L. Hafner, K. M. Mohiuddin, KK Rao, R. A. Becker-Szendy, T. M. Wong, O. A. Zaki, M. Hernandez, K. R. Fernandez, H. Huels, H. Lenk, K. Smolin, M. Ries, C. Goettert, T. Picunko, B. J. Rubin, H. Kahn, and T. Loo
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p. 181
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Reliability of modular mesh-connected intelligent storage brick systems
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C. Fleiner, R. B. Garner, J. L. Hafner, KK Rao, D. R. Kenchammana-Hosekote, W. W. Wilcke, and J. S. Glider
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p. 199
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Using and managing large systems
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Braids and fibers: Language constructs with architectural support for adaptive responses to memory latencies
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D. F. Bacon and X. Shen
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p. 209
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Self-adapting numerical software (SANS) effort
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J. Dongarra, G. Bosilca, Z. Chen, V. Eijkhout, G. E. Fagg, E. Fuentes, J. Langou, P. Luszczek, J. Pjesivac-Grbovic, K. Seymour, H. You, and S. S. Vadhiyar
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p. 223
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Performance and environment monitoring for continuous program optimization
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C. Caşcaval, E. Duesterwald, P. F. Sweeney, and R. W. Wisniewski
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p. 239
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Building web services for scientific grid applications
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G. Kandaswamy, L. Fang, Y. Huang, S. Shirasuna, S. Marru, and D. Gannon
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p. 249
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HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection
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R. Shetty, M. Kharbutli, Y. Solihin, and M. Prvulovic
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p. 261
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Processors, circuits, architecture, tools
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Limited switch dynamic logic circuits for high-speed low-power circuit design
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W. Belluomini, D. Jamsek, A. K. Martin, C. McDowell, R. K. Montoye, H. C. Ngo, and J. Sawada
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p. 277
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Decomposing the load–store queue by function for power reduction and scalability
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L. Baugh and C. Zilles
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p. 287
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High-quality ISA synthesis for low-power cache designs in embedded microprocessors
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A. C. Cheng and G. S. Tyson
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p. 299
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Modeling wire delay, area, power, and performance in a simulation infrastructure
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N. P. Carter and A. Hussain
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p. 311
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Application of full-system simulation in exploratory system design and development
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J. L. Peterson, P. J. Bohrer, L. Chen, E. N. Elnozahy, A. Gheith, R. H. Jewell, M. D. Kistler, T. R. Maeurer, S. A. Malone, D. B. Murrell, N. Needel, K. Rajamani, M. A. Rinaldi, R. O. Simpson, K. Sudeep, and L. Zhang
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p. 321
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Erratum
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p. 333
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