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IBM Journal of Research and Development

POWER5 and Packaging Volume 49, Number 4/5, 2005 Click to enlarge
RD 49-4/5
Two new microprocessors, POWER5 and the Cell, are described in the first section of this double issue. Papers included are on POWER5 system architecture, virtualization, operating systems, design verification, and performance. Also included is an overview paper on the Cell (or STI) project. The second section of this issue discusses advanced packaging for microelectronics. Topics include lead-free alloy solders, injection-molded microbumps for interconnections, use of organics in packaging, advanced testing techniques, system-on-a-package, optical interconnects, and a reexamination of Rent’s rule.
Table of Contents Papers in:     Order No. G322-0244-00
POWER5
Preface Joel M. Tendler, Program Director, Technology Assessment, IBM Systems and Technology Group p. 503
POWER5 system microarchitecture B. Sinharoy, R. N. Kalla, J. M. Tendler, R. J. Eickemeyer, and J. B. Joyner p. 505
Advanced virtualization capabilities of POWER5 systems W. J. Armstrong, R. L. Arndt, D. C. Boutcher, R. G. Kovacs, D. Larson, K. A. Lucke, N. Nayar, and R. C. Swanberg p. 523
Operating system exploitation of the POWER5 system P. Mackerras, T. S. Mathews, and R. C. Swanberg p. 533
Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems D. W. Victor, J. M. Ludden, R. D. Peterson, B. S. Nelson, W. K. Sharp, J. K. Hsu, B.-L. Chu, M. L. Behm, R. M. Gott, A. D. Romonosky, and S. R. Farago p. 541
Characterization of simultaneous multithreading (SMT) efficiency in POWER5 H. M. Mathis, A. E. Mericas, J. D. McCalpin, R. J. Eickemeyer, and S. R. Kunkel p. 555
Functional formal verification on designs of pSeries microprocessors and communication subsystems R. M. Gott, J. R. Baumgartner, P. Roessler, and S. I. Joe p. 565
Using microcode in the functional verification of an I/O chip S. P. Goldman, L. M. Mohr, and D. R. Smith p. 581
Introduction to the Cell multiprocessor J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy p. 589
Packaging
Preface Katharine G. Frase, VP, Worldwide Packaging and Test, IBM Systems and Technology Group, and David E. Seeger, Division Group Manager, Electronic and Optical Packaging, IBM Research Division p. 605
Microstructure and mechanical properties of lead-free solders and solder joints used in microelectronic applications S. K. Kang, P. A. Lauro, D.-Y. Shih, D. W. Henderson, and K. J. Puttlitz p. 607
Low-cost wafer bumping P. A. Gruber, L. Bélanger, G. P. Brouillette, D. H. Danovitch, J.-L. Landreville, D. T. Naugle, V. A. Oberson, D.-Y. Shih, C. L. Tessler, and M. R. Turgeon p. 621
The evolution of build-up package technology and its design challenges E. D. Blackshear, M. Cases, E. Klink, S. R. Engle, R. S. Malfatt, D. N. de Araujo, S. Oggioni, L. D. Lacroix, J. A. Wakil, N. H. Pham, G. G. Hougham, and D. J. Russell p. 641
Effects of mechanical stress and moisture on packaging interfaces S. L. Buchwalter, P. J. Brofman, C. Feger, M. A. Gaynes, K.-W. Lee, L. J. Matienzo, and D. L. Questad p. 663
Latent defect screening for high-reliability glass-ceramic multichip module copper interconnects E. J. Yarmchuk, C. W. Cline, and D. C. Bruen p. 677
High-speed electrical testing of multichip ceramic modules D. G. Manzer, J. P. Karidis, K. M. Wiley, D. C. Bruen, C. W. Cline, C. Hendricks, R. N. Wiggin, and Y.-Y. Yu p. 687
Mixing, rheology, and stability of highly filled thermal pastes C. Feger, J. D. Gelorme, M. McGlashan-Powell, and D. M. Kalyon p. 699
Challenges of data center thermal management R. R. Schmidt, E. E. Cruz, and M. K. Iyengar p. 709
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection J. U. Knickerbocker, P. S. Andry, L. P. Buchwalter, A. Deutsch, R. R. Horton, K. A. Jenkins, Y. H. Kwark, G. McVicker, C. S. Patel, R. J. Polastre, C. Schuster, A. Sharma, S. M. Sri-Jayantha, C. W. Surovic, C. K. Tsang, B. C. Webb, S. L. Wright, S. R. McKnight, E. J. Sprogis, and B. Dang p. 725
Exploitation of optical interconnects in future server architectures A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter p. 755
Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements M. Y. Lanzerotti, G. Fiorenza, and R. A. Rand p. 777

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