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Two new microprocessors, POWER5 and the Cell, are described in the first section of this double issue. Papers included are on POWER5 system architecture, virtualization, operating systems, design verification, and performance. Also included is an overview paper on the Cell (or STI) project. The second section of this issue discusses advanced packaging for microelectronics. Topics include lead-free alloy solders, injection-molded microbumps for interconnections, use of organics in packaging, advanced testing techniques, system-on-a-package, optical interconnects, and a reexamination of Rent’s rule.
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POWER5
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Preface
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Joel M. Tendler, Program Director, Technology Assessment, IBM Systems and Technology Group
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p. 503
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POWER5 system microarchitecture
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B. Sinharoy, R. N. Kalla, J. M. Tendler, R. J. Eickemeyer, and J. B. Joyner
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p. 505
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Advanced virtualization capabilities of POWER5 systems
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W. J. Armstrong, R. L. Arndt, D. C. Boutcher, R. G. Kovacs, D. Larson, K. A. Lucke, N. Nayar, and R. C. Swanberg
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p. 523
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Operating system exploitation of the POWER5 system
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P. Mackerras, T. S. Mathews, and R. C. Swanberg
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p. 533
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Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems
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D. W. Victor, J. M. Ludden, R. D. Peterson, B. S. Nelson, W. K. Sharp, J. K. Hsu, B.-L. Chu, M. L. Behm, R. M. Gott, A. D. Romonosky, and S. R. Farago
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p. 541
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Characterization of simultaneous multithreading (SMT) efficiency in POWER5
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H. M. Mathis, A. E. Mericas, J. D. McCalpin, R. J. Eickemeyer, and S. R. Kunkel
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p. 555
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Functional formal verification on designs of pSeries microprocessors and communication subsystems
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R. M. Gott, J. R. Baumgartner, P. Roessler, and S. I. Joe
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p. 565
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Using microcode in the functional verification of an I/O chip
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S. P. Goldman, L. M. Mohr, and D. R. Smith
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p. 581
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Introduction to the Cell multiprocessor
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J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy
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p. 589
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Packaging
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Preface
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Katharine G. Frase, VP, Worldwide Packaging and Test, IBM Systems and Technology Group, and David E. Seeger, Division Group Manager, Electronic and Optical Packaging, IBM Research Division
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p. 605
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Microstructure and mechanical properties of lead-free solders and solder joints used in microelectronic applications
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S. K. Kang, P. A. Lauro, D.-Y. Shih, D. W. Henderson, and K. J. Puttlitz
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p. 607
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Low-cost wafer bumping
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P. A. Gruber, L. Bélanger, G. P. Brouillette, D. H. Danovitch, J.-L. Landreville, D. T. Naugle, V. A. Oberson, D.-Y. Shih, C. L. Tessler, and M. R. Turgeon
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p. 621
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The evolution of build-up package technology and its design challenges
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E. D. Blackshear, M. Cases, E. Klink, S. R. Engle, R. S. Malfatt, D. N. de Araujo, S. Oggioni, L. D. Lacroix, J. A. Wakil, N. H. Pham, G. G. Hougham, and D. J. Russell
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p. 641
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Effects of mechanical stress and moisture on packaging interfaces
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S. L. Buchwalter, P. J. Brofman, C. Feger, M. A. Gaynes, K.-W. Lee, L. J. Matienzo, and D. L. Questad
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p. 663
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Latent defect screening for high-reliability glass-ceramic multichip module copper interconnects
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E. J. Yarmchuk, C. W. Cline, and D. C. Bruen
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p. 677
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High-speed electrical testing of multichip ceramic modules
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D. G. Manzer, J. P. Karidis, K. M. Wiley, D. C. Bruen, C. W. Cline, C. Hendricks, R. N. Wiggin, and Y.-Y. Yu
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p. 687
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Mixing, rheology, and stability of highly filled thermal pastes
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C. Feger, J. D. Gelorme, M. McGlashan-Powell, and D. M. Kalyon
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p. 699
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Challenges of data center thermal management
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R. R. Schmidt, E. E. Cruz, and M. K. Iyengar
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p. 709
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Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
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J. U. Knickerbocker, P. S. Andry, L. P. Buchwalter, A. Deutsch, R. R. Horton, K. A. Jenkins, Y. H. Kwark, G. McVicker, C. S. Patel, R. J. Polastre, C. Schuster, A. Sharma, S. M. Sri-Jayantha, C. W. Surovic, C. K. Tsang, B. C. Webb, S. L. Wright, S. R. McKnight, E. J. Sprogis, and B. Dang
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p. 725
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Exploitation of optical interconnects in future server architectures
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A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, and M. B. Ritter
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p. 755
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Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements
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M. Y. Lanzerotti, G. Fiorenza, and R. A. Rand
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p. 777
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