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Scaling CMOS to the limit

Vol. 46, No. 2/3, 2002

Order No. G322-0231
 
This double issue contains fifteen papers which address the challenges of scaling CMOS devices as physical limits are approached. There are papers on CMOS logic technology, including silicon-on-insulator (SOI), and dynamic random-access memory (DRAM) technology, as well as a proposed CMOS-compatible bipolar technology for analog applications. The reliability of the gate dielectric, and the evolution of devices, processes, and materials are addressed, including new device and material options. Progressing from device to system, the issue includes papers on power dissipation in the context of device limits, interconnect scaling, and the question of how to use the billions of transistors projected for future chips.
RD46-23
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Papers on Scaling CMOS to the limit
Preface Paul M. Solomon, Guest Editor p. 119
SOI technology for the GHz era G. G. Shahidi p. 121
Beyond the conventional transistor H.-S. P. Wong p. 133
Maintaining the benefits of CMOS scaling when scaling bogs down E. J. Nowak p. 169
Why BiCMOS and SOI BiCMOS? T. H. Ning p. 181
Challenges and future directions for the scaling of dynamic random-access memory (DRAM) J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. Divakaruni, Y. Li, and C. J. Radens p. 187
CMOS design near the limit of scaling Y. Taur p. 213
Effect of increasing chip density on the evolution of computer architectures R. Nair p. 223
Power-constrained CMOS scaling limits D. J. Frank p. 235
Interconnect opportunities for gigascale integration J. D. Meindl, J. A. Davis, P. Zarkesh-Ha, C. S. Patel, K. P. Martin, and P. A. Kohl p. 245
Reliability limits for the gate insulator in CMOS technology J. H. Stathis p. 265
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics E. Y. Wu, E. J. Nowak, A. Vayshenker, W. L. Lai, and D. L. Harmon p. 287
Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? C. M. Osburn, I. Kim, S. K. Han, I. De, K. F. Yee, S. Gannavaram, S. J. Lee,
C.-H. Lee, Z. J. Luo, W. Zhu, J. R. Hauser, D.-L. Kwong, G. Lucovsky, T. P. Ma, and M. C. Öztürk
p. 299
Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation P. D. Agnello p. 317
Process modeling for future technologies M. E. Law p. 339
New insights into carrier transport in n-MOSFETs A. Lochtefeld, I. J. Djomehri, G. Samudra, and D. A. Antoniadis p. 347
Preparation of manuscripts for the IBM Journal of Research and Development   p. 359