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IBM POWER4 System

Vol. 46, No. 1, 2002

Order No. G322-0230
 
This issue contains five papers on the design of the IBM POWER4 Microprocessor and its use in the IBM eServer p690 "Regatta" system. Included are papers on the microarchitecture, circuit and physical design, fault-tolerant design, and functional verification of POWER4, and a paper describing the management and information-handling infrastructure for this large-scale multi-site development project. Also in the issue is a paper on pseudorandom-number generation using the fused multiply–add capabilities of IBM RISC-based processors.
RD46-1
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Papers on the IBM POWER4 System
Preface Vijay T. Lund, Vice President, eServer Technology Development, IBM Server Group p. 3
POWER4 system microarchitecture J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy p. 5
The circuit and physical design of the POWER4 microprocessor J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, and C. J. Anderson p. 27
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson,
B.-L. Chu, M. L. Behm, J. R. Baumgartner, R. D. Peterson, J. Abdulhafiz, W. E. Bucy, J. H. Klaus, D. J. Klema, T. N. Le, F. D. Lewis, P. E. Milling, L. A. McConville, B. S. Nelson, V. Paruthi, T. W. Pouarz, A. D. Romonosky, J. Stuecheli, K. D. Thompson, D. W. Victor, and B. Wile
p. 53
Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology D. C. Bossen, A. Kitamorn, K. F. Reick, and M. S. Floyd p. 77
Infrastructure requirements for a large-scale, multi-site VLSI development project G. P. Rodgers, I. G. Bendrihem, T. J. Bucelot, B. D. Burchett, and J. C. Collins p. 87
Regular papers
Fast pseudorandom-number generators with modulus 2k or 2k – 1 using fused multiply–add R. C. Agarwal, R. F. Enenkel, F. G. Gustavson, A. Kothari, and M. Zubair p. 97