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IBM CMOS Technology

Vol. 39, No. 1/2, 1995

Order No. G322-0196
Within the past decade CMOS has become the technology of choice for a broad range of semiconductor products. High-density DRAMs, high-speed processors, and low-power devices for mobile applications are key examples. This issue of the IBM Journal of Research and Development is a collection of papers on IBM CMOS technology which illustrates this breadth of application and describes the increasing sophistication that is present in the underlying design tools and fabrication techniques.
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Please note: All papers are available in PDF format. A feature paper and abstracts are available in HTML.
Table of contents
Papers may be viewed by clicking on the title of interest
Preface D. J. Fleming p. 3
Design at the system level with VLSI CMOS R. F. Sechler and G. F. Grohoski p. 5
Interconnect design with VLSI CMOS R. F. Sechler p. 23
Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor K. Bernstein, J. E. Bertsch, L. G. Heller, E. J. Nowak, and F. R. White p. 33
A 64Kb × 32 DRAM for graphics applications T. Sunaga, K. Hosokawa, S. H. Dhong, and K. Kitamura p. 43
Multipurpose DRAM architecture for optimal power, performance, and product flexibility W. F. Ellis, J. E. Barth, Jr., S. Divakaruni, J. H. Dreibelbis, A. Furman, E. L. Hedberg, H. S. Lee, T. M. Maffitt, C. P. Miller, C. H. Stapper, and H. L. Kalter p. 51
Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier D. M. Kuchta, H. A. Ainspan, F. J. Canora, and R. P. Schneider, Jr. p. 63
CMOS circuits for Gb/s serial data communication J. F. Ewen, M. Soyuer, A. X. Widmer, K. R. Wrenner, B. D. Parker, and H. A. Ainspan p. 73
Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications H. J. Shin, D. J. Pearson, S. K. Reynolds, A. C. Megdanis, S. Gowda, and K. R. Wrenner p. 83
Digital delay line clock shapers and multipliers R. A. Bechade and R. M. Houle p. 93
A low-noise TTL-compatible CMOS off-chip driver circuit S. H. Dhong, M. Tanaka, S. W. Tomashot, and T. Kirihata p. 105
Architectural timing verification of CMOS RISC processors P. Bose and S. Surya p. 113
High-level synthesis in an industrial environment R. A. Bergamaschi, R. A. O'Connor, L. Stok, M. Z. Moricz, S. Prakash, A. Kuehlmann, and D. S. Rao p. 131
Verity—A formal verification program for custom CMOS circuits A. Kuehlmann, A. Srinivasan, and D. P. LaPotin p. 149
Feature paper The evolution of IBM CMOS DRAM technology E. Adler, J. K. DeBrosse, S. F. Geissler, S. J. Holmes, M. D. Jaffe, J. B. Johnson, C. W. Koburger III, J. B. Lasky, B. Lloyd, G. L. Miles, J. S. Nakos, W. P. Noble, Jr., S. H. Voldman, M. Armacost, and R. Ferguson p. 167
Overview of gate linewidth control in the manufacture of CMOS logic chips D. G. Chesebro, J. W. Adkisson, L. R. Clark, S. N. Eslinger, M. A. Faucher, S. J. Holmes, R. P. Mallette, E. J. Nowak, E. W. Sengle, S. H. Voldman, and T. W. Weeks p. 189
Integrated cost and productivity learning in CMOS semiconductor manufacturing G. A. Leonovich, A. P. Franchino, W. J. Miller, and U. E. Tsou p. 201
A half-micron CMOS logic generation C. W. Koburger III, W. F. Clark, J. W. Adkisson, E. Adler, P. E. Bakeman, A. S. Bergendahl, A. B. Botula, W. Chang, B. Davari, J. H. Givens, H. H. Hansen, S. J. Holmes, D. V. Horak, C. H. Lam, J. B. Lasky, S. E. Luce, R. W. Mann, G. L. Miles J. S. Nakos, E. J. Nowak, G. Shahidi, Y. Taur, F. R. White, and M. R. Wordeman p. 215
CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications G. G. Shahidi, J. D. Warnock, J. Comfort, S. Fischer, P. A. McFarland, A. Acovic, T. I. Chappell, B. A. Chappell, T. H. Ning, C. J. Anderson, R. H. Dennard, J. Y. Sun, M. R. Polcari, and B. Davari p. 229
CMOS scaling into the 21st century: 0.1 µm and beyond Y. Taur, Y. J. Mii, D. J. Frank, H. S. Wong, D. A. Buchanan, S. J. Wind, S. A. Rishton, G. A. Sai-Halasz, and E. J. Nowak p. 245
Recent publications by IBM authors p. 261
Recent IBM patents p. 275