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IBM Journal of Research and Development
Soft Errors in Circuits and Systems   Volume 52, Number 3, 2008
Table of contents: HTMLPDF This article: HTMLPDF   Copyright info

Phaser: Phased methodology for modeling the system-level effects of soft errors - References

 by J. A. Rivers,
P. Bose,
P. Kudva,
J.-D. Wellman,
P. N. Sanda,
E. H. Cannon,
and L. C. Alves
References

  1. S. Borkar, “Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation,” IEEE Micro 25, No. 6, 10–16 (2005).
  2. A. KleinOsowski, E. H. Cannon, P. Oldiges, and L. Wissel, “Circuit Design and Modeling for Soft Errors,” IBM J. Res. & Dev. 52, No. 3, 255–263 (2008, this issue).
  3. M. E. Wazlowski, N. R. Adiga, D. K. Beece, R. Bellofatto, M. A. Blumrich, D. Chen, M. B. Dombrowa, et al., “Verification Strategy for the Blue Gene/L Chip,” IBM J. Res. & Dev. 49, No. 2/3, 303–318 (2005).
  4. J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B.-L. Chu, M. L. Behm, et al., “Functional Verification of the POWER4 Microprocessor and POWER4 Multiprocessor Systems,” IBM J. Res. & Dev. 46, No. 1, 53–76 (2002).
  5. P. N. Sanda, J. W. Kellington, P. Kudva, R. Kalla, R. B. McBeth, J. Ackaret, R. Lockwood, J. Schumann, and C. R. Jones, “Soft-Error Resilience of the IBM POWER6 Processor,” IBM J. Res. & Dev. 52, No. 3, 275–284 (2008, this issue).
  6. X. Li, S. V. Adve, P. Bose, and J. A. Rivers, “SoftArch: An Architecture-Level Tool for Modeling and Analyzing Soft Errors,” Proceedings of the International Conference on Dependable Systems and Networks, Yokohama, Japan, 2005, pp. 496–505.
  7. X Li, S. V. Adve, P. Bose, and J. A. Rivers, “Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions,” Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, Edinburgh, U.K., 2007, pp. 266–275.
  8. S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin, “A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor,” Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, San Diego, CA, 2003, pp. 29–40.
  9. A. Biswas, P. Racunas, R. Cheveresan, J. Emer, S. S. Mukherjee, and R. Rangan, “Computing Architectural Vulnerability Factors for Address-Based Structures,” Proceedings of the 32nd International Symposium on Computer Architecture, Madison, WI, 2005, pp. 532–543.
  10. P. Kudva, B. Curran, S. K. Karandikar, M. Mayo, S. Carey, and S. S. Sapatnekar, “Early Performance Prediction,” Proceedings of the Workshop on Complexity—Effective Design: Held in Conjunction with the 32nd International Symposium on Computer Architecture, Madison, WI, 2005; see http://www.csl.cornell.edu/~albonesi/wced05/wced05.pdf.
  11. H. Q. Le, W. J. Starke, J. S. Fields, F. P. O'Connell, D. Q. Nguyen, B. J. Ronchetti, W. M. Sauer, E. M. Schwarz, and M. T. Vaden, “IBM POWER6 Microarchitecture,” IBM J. Res. & Dev. 51, No. 6, pp. 639–662 (2007).
  12. G. P. Saggese, N. J. Wang, Z. T. Kalbarczyk, S. J. Patel, and R. K. Iyer, “An Experimental Study of Soft Errors in Microprocessors,” IEEE Microprocessors 25, No. 6, 30–39 (2005).
  13. P. Kudva, J. W. Kellington, P. N. Sanda, R. McBeth, J. Schumann, and R. Kalla, “Fault Injection Verification of IBM POWER6 Soft Error Resilience,” Proceedings of the Workshop on Architectural Support for Gigascale Integration, San Diego, CA, 2007; see http://www.ece.cmu.edu/~asgi/F4.pdf.
  14. P. Bose, “Testing for Function and Performance: Towards an Integrated Processor Validation Methodology,” J. Electronic Testing Theory Application 16, No. 1/2, 29–48 (2000).


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