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IBM Journal of Research and Development
IBM POWER6 Microprocessor Technology   Volume 51, Number 6, 2007
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IBM POWER6 SRAM arrays - References

 by D. W. Plass
and Y. H. Chan
References

  1. K. J. Kim, J. M. Youn, S. B. Kim, J. H. Kim, S. H. Hwang, K. T. Kim, and Y. S. Shin, “A Novel 6.4 μm2 Full-CMOS SRAM Cell with Aspect Ratio of 0.63 in a High-Performance 0.25 μm-Generation CMOS Technology,” 1998 Symposium on VLSI Technology, Digest of Technical Papers, June 9–11, 1998, pp. 68–69.
  2. S. Nakai, M. Kojima, N. Misawa, M. Miyajima, S. Asai, S. Inagaki, Y. Iba, et al., “A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55 μm2 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications,” IEEE International Electron Devices Meeting, Technical Digest, December 8–10, 2003, pp. 285–288.
  3. B. W. Curran, Y. H. Chan, P. T. Wu, P. J. Camprese, G. A. Northrop, R. F. Hatch, L. B. Lacey, J. P. Eckhardt, D. T. Hui, and H. H. Smith, “IBM eServer z900 High-Frequency Microprocessor Technology, Circuits, and Design Methodology,” IBM J. Res. & Dev. 46, No. 4/5, pp. 631–644 (2002).
  4. A. R. Pelella, A. D. Tuminaro, R. T. Freese, and Y. H. Chan, “A 8Kb Domino Read SRAM with Hit Logic and Parity Checkers,” Proceedings of the 31st European Solid-State Circuits Conference, September 12–16, 2005, pp. 359–362.
  5. J. Davis, D. Plass, P. Bunce, Y. Chan, A. Pelella, R. Joshi, A. Chen, et al., “A 5.6GHz 64kB Dual-Read Data Cache for the POWER6™ Processor,” Solid-States Circuits, 2006 IEEE International Conference, Digest of Technical Papers, San Francisco, CA, February 5–9, 2006, pp. 622–623.
  6. J. Wuu, D. Weiss, C. Morganti, and M. Dreesen, “The Asynchronous 24MB On-Chip Level-3 Cache for a Dual-Core Itanium®-Family Processor,” International Solid-States Conference, Digest of Technical Papers, February 6–10, 2005, pp. 488–489.


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